diff options
| author | Dinh Nguyen <dinguyen@kernel.org> | 2021-06-11 05:52:00 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2021-06-28 02:39:59 +0300 |
| commit | c2c9c5661a48bf2e67dcb4e989003144304acd6a (patch) | |
| tree | ecf6cd99a5031c2dcf5f48220f8f6ec70ca88542 /drivers/clk/socfpga/stratix10-clk.h | |
| parent | 6855ee839699bdabb4b16cf942557fd763bcb1fa (diff) | |
| download | linux-c2c9c5661a48bf2e67dcb4e989003144304acd6a.tar.xz | |
clk: agilex/stratix10: add support for the 2nd bypass
The EMAC clocks on Stratix10/Agilex/N5X have an additional bypass that
was not being accounted for. The bypass selects between
emaca_clk/emacb_clk and boot_clk.
Because the bypass register offset is different between Stratix10 and
Agilex/N5X, it's best to create a new function to calculate the bypass.
Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform")
Cc: stable@vger.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20210611025201.118799-3-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/socfpga/stratix10-clk.h')
| -rw-r--r-- | drivers/clk/socfpga/stratix10-clk.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/socfpga/stratix10-clk.h b/drivers/clk/socfpga/stratix10-clk.h index 61eaf3a41fbb..75234e0783e1 100644 --- a/drivers/clk/socfpga/stratix10-clk.h +++ b/drivers/clk/socfpga/stratix10-clk.h @@ -85,4 +85,6 @@ struct clk_hw *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *c void __iomem *reg); struct clk_hw *s10_register_gate(const struct stratix10_gate_clock *clks, void __iomem *reg); +struct clk_hw *agilex_register_gate(const struct stratix10_gate_clock *clks, + void __iomem *reg); #endif /* __STRATIX10_CLK_H */ |