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authorJernej Skrabec <jernej.skrabec@siol.net>2018-03-02 00:34:30 +0300
committerMaxime Ripard <maxime.ripard@bootlin.com>2018-03-02 10:42:30 +0300
commit55de0f31df1a31b346edfe98d061f11162ff1ad4 (patch)
tree89a6fb0dccd43e1e06aa8dc451bdbe5512d53617 /drivers/clk/sunxi-ng
parentb1a1ad4b75b876ccf200f2351ae61364bf856613 (diff)
downloadlinux-55de0f31df1a31b346edfe98d061f11162ff1ad4.tar.xz
clk: sunxi-ng: h3: h5: export CLK_PLL_VIDEO
CLK_PLL_VIDEO needs to be referenced in HDMI DT entry as a possible PHY clock parent. Export it so it can be used later in DT. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'drivers/clk/sunxi-ng')
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-h3.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.h b/drivers/clk/sunxi-ng/ccu-sun8i-h3.h
index 1b4baea37d81..73d7392c968c 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.h
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.h
@@ -26,7 +26,9 @@
#define CLK_PLL_AUDIO_2X 3
#define CLK_PLL_AUDIO_4X 4
#define CLK_PLL_AUDIO_8X 5
-#define CLK_PLL_VIDEO 6
+
+/* PLL_VIDEO is exported */
+
#define CLK_PLL_VE 7
#define CLK_PLL_DDR 8