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authorPeter De Schrijver <pdeschrijver@nvidia.com>2013-09-02 16:22:02 +0400
committerPeter De Schrijver <pdeschrijver@nvidia.com>2013-11-26 20:46:18 +0400
commit343a607cb79259429afbb9820bf524d33084e66c (patch)
tree508757a525821d7aad6c6d24caa72447c95907bf /drivers/clk/tegra/clk-tegra20.c
parentd5ff89a82a6d272d210db68a9487877682c94a24 (diff)
downloadlinux-343a607cb79259429afbb9820bf524d33084e66c.tar.xz
clk: tegra: common periph_clk_enb_refcnt and clks
This patch makes periph_clk_enb_refcnt a global array, dynamically allocated at boottime. It simplifies the macros somewhat and allows clocks common to several Tegra SoCs to be defined in a separate files. Also the clks array becomes global and dynamically allocated which allows the DT registration to be moved to a generic funcion. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-tegra20.c')
-rw-r--r--drivers/clk/tegra/clk-tegra20.c36
1 files changed, 9 insertions, 27 deletions
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 929a46278d83..6bf5c339ab43 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -25,8 +25,6 @@
#include "clk.h"
-#define CLK_OUT_ENB_NUM 3
-
#define OSC_CTRL 0x50
#define OSC_CTRL_OSC_FREQ_MASK (3<<30)
#define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
@@ -170,8 +168,6 @@ static struct cpu_clk_suspend_context {
} tegra20_cpu_clk_sctx;
#endif
-static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
-
static void __iomem *clk_base;
static void __iomem *pmc_base;
@@ -182,21 +178,21 @@ static DEFINE_SPINLOCK(sysrate_lock);
_clk_num, _gate_flags, _clk_id) \
TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
- _clk_num, periph_clk_enb_refcnt, \
+ _clk_num, \
_gate_flags, _clk_id)
#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \
_clk_num, _gate_flags, _clk_id) \
TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT, \
- _clk_num, periph_clk_enb_refcnt, _gate_flags, \
+ _clk_num, _gate_flags, \
_clk_id)
#define TEGRA_INIT_DATA_DIV16(_name, _con_id, _dev_id, _parents, _offset, \
_clk_num, _gate_flags, _clk_id) \
TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \
- _clk_num, periph_clk_enb_refcnt, _gate_flags, \
+ _clk_num, _gate_flags, \
_clk_id)
#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \
@@ -204,7 +200,7 @@ static DEFINE_SPINLOCK(sysrate_lock);
_gate_flags, _clk_id) \
TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
_mux_shift, _mux_width, 0, 0, 0, 0, 0, \
- _clk_num, periph_clk_enb_refcnt, _gate_flags, \
+ _clk_num, _gate_flags, \
_clk_id)
/* IDs assigned here must be in sync with DT bindings definition
@@ -226,8 +222,7 @@ enum tegra20_clk {
pll_x, cop, audio, pll_ref, twd, clk_max,
};
-static struct clk *clks[clk_max];
-static struct clk_onecell_data clk_data;
+static struct clk **clks;
static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
{ 12000000, 600000000, 600, 12, 0, 8 },
@@ -808,7 +803,7 @@ static struct tegra_periph_init_data tegra_periph_clk_list[] = {
TEGRA_INIT_DATA_DIV16("i2c3", "div-clk", "tegra-i2c.2", mux_pllpcm_clkm, CLK_SOURCE_I2C3, 67, TEGRA_PERIPH_ON_APB, i2c3),
TEGRA_INIT_DATA_DIV16("dvc", "div-clk", "tegra-i2c.3", mux_pllpcm_clkm, CLK_SOURCE_DVC, 47, TEGRA_PERIPH_ON_APB, dvc),
TEGRA_INIT_DATA_MUX("hdmi", NULL, "hdmi", mux_pllpdc_clkm, CLK_SOURCE_HDMI, 51, 0, hdmi),
- TEGRA_INIT_DATA("pwm", NULL, "tegra-pwm", pwm_parents, CLK_SOURCE_PWM, 28, 3, 0, 0, 8, 1, 0, 17, periph_clk_enb_refcnt, TEGRA_PERIPH_ON_APB, pwm),
+ TEGRA_INIT_DATA("pwm", NULL, "tegra-pwm", pwm_parents, CLK_SOURCE_PWM, 28, 3, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, pwm),
};
static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
@@ -1232,7 +1227,6 @@ static const struct of_device_id pmc_match[] __initconst = {
static void __init tegra20_clock_init(struct device_node *np)
{
- int i;
struct device_node *node;
clk_base = of_iomap(np, 0);
@@ -1253,7 +1247,8 @@ static void __init tegra20_clock_init(struct device_node *np)
BUG();
}
- if (tegra_clk_set_periph_banks(TEGRA20_CLK_PERIPH_BANKS) < 0)
+ clks = tegra_clk_init(clk_max, TEGRA20_CLK_PERIPH_BANKS);
+ if (!clks)
return;
tegra20_osc_clk_init();
@@ -1264,22 +1259,9 @@ static void __init tegra20_clock_init(struct device_node *np)
tegra20_periph_clk_init();
tegra20_audio_clk_init();
-
- for (i = 0; i < ARRAY_SIZE(clks); i++) {
- if (IS_ERR(clks[i])) {
- pr_err("Tegra20 clk %d: register failed with %ld\n",
- i, PTR_ERR(clks[i]));
- BUG();
- }
- if (!clks[i])
- clks[i] = ERR_PTR(-EINVAL);
- }
-
tegra_init_dup_clks(tegra_clk_duplicates, clks, clk_max);
- clk_data.clks = clks;
- clk_data.clk_num = ARRAY_SIZE(clks);
- of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+ tegra_add_of_provider(np);
tegra_clk_apply_init_table = tegra20_clock_apply_init_table;