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| author | Dmitry Osipenko <digetx@gmail.com> | 2021-11-15 01:07:58 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2021-12-15 18:39:15 +0300 |
| commit | e360e116a0eec9cf719cda5860e95d36606687e7 (patch) | |
| tree | 4563cdc69ec9744791843f0eb2ebf3593c3e127e /drivers/clk/tegra/clk-tegra30.c | |
| parent | fa55b7dcdc43c1aa1ba12bca9d2dd4318c2a0dbf (diff) | |
| download | linux-e360e116a0eec9cf719cda5860e95d36606687e7.tar.xz | |
clk: tegra: Make vde a child of pll_p on tegra114
The current default is to leave the VDE clock's parent at the default,
which is clk_m. However, that is not a configuration that will allow the
VDE to function. Reparent it to pll_p instead to make sure the hardware
can actually decode video content.
Tested-by: Anton Bambura <jenneron@protonmail.com> # ASUS TF701T
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-tegra30.c')
0 files changed, 0 insertions, 0 deletions