diff options
| author | Sowjanya Komatineni <skomatineni@nvidia.com> | 2019-08-16 22:42:00 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-11-11 16:53:04 +0300 |
| commit | 535f296d47de327287fe65b5843713bd9b01a267 (patch) | |
| tree | 73cabf151af02f59d0fb50a7e4848d04c080c0d6 /drivers/clk/tegra/clk.h | |
| parent | 3214be6cb1e487b0f8c3bb2eac9b06df07a07e06 (diff) | |
| download | linux-535f296d47de327287fe65b5843713bd9b01a267.tar.xz | |
clk: tegra: Add suspend and resume support on Tegra210
All the CAR controller settings are lost on suspend when core power goes
off. This implement saving and restoring context for all PLLs and clocks
during system suspend and resume to have the clocks back to same state
for normal operation.
Clock driver suspend and resume are registered as syscore_ops as clocks
restore need to happen before the other drivers resume to have all their
clocks back to the same state as before suspend.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk.h')
| -rw-r--r-- | drivers/clk/tegra/clk.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 3bb3d5f7b760..416a6b09f6a3 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -55,6 +55,20 @@ #define RST_DEVICES_SET_Y 0x2a8 #define RST_DEVICES_CLR_Y 0x2ac +/* + * Tegra CLK_OUT_ENB registers have some undefined bits which are not used and + * any accidental write of 1 to these bits can cause PSLVERR. + * So below are the valid mask defines for each CLK_OUT_ENB register used to + * turn ON only the valid clocks. + */ +#define TEGRA210_CLK_ENB_VLD_MSK_L 0xdcd7dff9 +#define TEGRA210_CLK_ENB_VLD_MSK_H 0x87d1f3e7 +#define TEGRA210_CLK_ENB_VLD_MSK_U 0xf3fed3fa +#define TEGRA210_CLK_ENB_VLD_MSK_V 0xffc18cfb +#define TEGRA210_CLK_ENB_VLD_MSK_W 0x793fb7ff +#define TEGRA210_CLK_ENB_VLD_MSK_X 0x3fe66fff +#define TEGRA210_CLK_ENB_VLD_MSK_Y 0xfc1fc7ff + /** * struct tegra_clk_sync_source - external clock source from codec * @@ -880,6 +894,8 @@ int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width, u8 frac_width, u8 flags); void tegra_clk_osc_resume(void __iomem *clk_base); void tegra_clk_set_pllp_out_cpu(bool enable); +void tegra_clk_periph_suspend(void); +void tegra_clk_periph_resume(void); /* Combined read fence with delay */ |