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| author | Konrad Dybcio <konrad.dybcio@linaro.org> | 2023-06-14 14:35:33 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2023-09-13 10:42:45 +0300 |
| commit | 9cba16beca66ad2e66e3a5952f2ccff98375d4fd (patch) | |
| tree | 7a755bd67fdcd0b229b2523e084509f0822ae785 /drivers/clk | |
| parent | 6ace98cb617bafb506c8b76a98e91e3051271494 (diff) | |
| download | linux-9cba16beca66ad2e66e3a5952f2ccff98375d4fd.tar.xz | |
clk: qcom: gpucc-sm6350: Fix clock source names
[ Upstream commit 743913b343a3ec2510fe3c0dfaff03d049659922 ]
fw_name for GCC inputs didn't match the bindings. Fix it.
Fixes: 013804a727a0 ("clk: qcom: Add GPU clock controller driver for SM6350")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230315-topic-lagoon_gpu-v2-2-afcdfb18bb13@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/qcom/gpucc-sm6350.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/qcom/gpucc-sm6350.c b/drivers/clk/qcom/gpucc-sm6350.c index a9887d1f0ed7..0bcbba2a2943 100644 --- a/drivers/clk/qcom/gpucc-sm6350.c +++ b/drivers/clk/qcom/gpucc-sm6350.c @@ -132,8 +132,8 @@ static const struct clk_parent_data gpu_cc_parent_data_0[] = { { .index = DT_BI_TCXO, .fw_name = "bi_tcxo" }, { .hw = &gpu_cc_pll0.clkr.hw }, { .hw = &gpu_cc_pll1.clkr.hw }, - { .index = DT_GPLL0_OUT_MAIN, .fw_name = "gcc_gpu_gpll0_clk" }, - { .index = DT_GPLL0_OUT_MAIN_DIV, .fw_name = "gcc_gpu_gpll0_div_clk" }, + { .index = DT_GPLL0_OUT_MAIN, .fw_name = "gcc_gpu_gpll0_clk_src" }, + { .index = DT_GPLL0_OUT_MAIN_DIV, .fw_name = "gcc_gpu_gpll0_div_clk_src" }, }; static const struct parent_map gpu_cc_parent_map_1[] = { @@ -151,7 +151,7 @@ static const struct clk_parent_data gpu_cc_parent_data_1[] = { { .hw = &gpu_cc_pll0.clkr.hw }, { .hw = &gpu_cc_pll1.clkr.hw }, { .hw = &gpu_cc_pll1.clkr.hw }, - { .index = DT_GPLL0_OUT_MAIN, .fw_name = "gcc_gpu_gpll0_clk" }, + { .index = DT_GPLL0_OUT_MAIN, .fw_name = "gcc_gpu_gpll0_clk_src" }, }; static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { |