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authorZhao Qiang <qiang.zhao@nxp.com>2020-09-16 06:03:10 +0300
committerStephen Boyd <sboyd@kernel.org>2020-10-14 05:48:09 +0300
commite9501b975a9efb499f2ecbe3374d433b25c5b4f4 (patch)
treecb0aab171fea024a8154e36cca142caa91bb6721 /drivers/clk
parent9123e3a74ec7b934a4a099e98af6a61c2f80bbf5 (diff)
downloadlinux-e9501b975a9efb499f2ecbe3374d433b25c5b4f4.tar.xz
clk: qoriq: modify MAX_PLL_DIV to 32
On LS2088A, Watchdog need clk divided by 32, so modify MAX_PLL_DIV to 32 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Link: https://lore.kernel.org/r/20200916030311.17280-1-qiang.zhao@nxp.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/clk-qoriq.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 5942e9874bc0..46101c6a20f2 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -31,7 +31,7 @@
#define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */
#define CGB_PLL1 4
#define CGB_PLL2 5
-#define MAX_PLL_DIV 16
+#define MAX_PLL_DIV 32
struct clockgen_pll_div {
struct clk *clk;