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authorStephen Boyd <sboyd@kernel.org>2020-10-20 21:46:47 +0300
committerStephen Boyd <sboyd@kernel.org>2020-10-20 21:46:47 +0300
commit3ab9a54f76e76c3b282c61451269bd614cd6cf52 (patch)
tree72f7f72d29a256bccbb3cfb4e723e456eb3e2059 /drivers/clk
parent9d3261628aa6338fe153d4d5d1e65f5caed87f01 (diff)
parenta2618360abd7dfebe18862860fcc44787874528e (diff)
parent6045124ebe722434bb52e89881c5fa41911c24f0 (diff)
parentf102ed0686b16a91473ad8ca4af8159b2d6bcb0a (diff)
parentb608f11d49ec671739604cc763248d8e8fadbbeb (diff)
parenta68224832118b32b0fd0226f7626b051c442125e (diff)
downloadlinux-3ab9a54f76e76c3b282c61451269bd614cd6cf52.tar.xz
Merge branches 'clk-simplify', 'clk-ti', 'clk-tegra', 'clk-rockchip' and 'clk-mediatek' into clk-next
- Small non-critical fixes for TI clk driver - Support Mediatek MT8167 clks * clk-simplify: clk: mediatek: fix platform_no_drv_owner.cocci warnings clk: mediatek: mt7629: simplify the return expression of mtk_infrasys_init clk: mediatek: mt6797: simplify the return expression of mtk_infrasys_init * clk-ti: clk: ti: dra7: add missing clkctrl register for SHA2 instance clk: ti: clockdomain: fix static checker warning clk: ti: autoidle: add checks against NULL pointer reference clk: keystone: sci-clk: add 10% slack to set_rate clk: keystone: sci-clk: cache results of last query rate operation clk: keystone: sci-clk: fix parsing assigned-clock data during probe * clk-tegra: clk: tegra: Drop !provider check in tegra210_clk_emc_set_rate() * clk-rockchip: clk: rockchip: Initialize hw to error to avoid undefined behavior clk: rockchip: rk3399: Support module build clk: rockchip: fix the clk config to support module build clk: rockchip: Export some clock common APIs for module drivers clk: rockchip: Export rockchip_register_softrst() clk: rockchip: Export rockchip_clk_register_ddrclk() clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls clk: rockchip: rk3308: drop unused mux_timer_src_p * clk-mediatek: clk: mediatek: Add MT8167 clock support dt-bindings: clock: mediatek: add bindings for MT8167 clocks clk: mediatek: add UART0 clock support