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authorDinh Nguyen <dinguyen@altera.com>2014-02-20 01:11:10 +0400
committerMike Turquette <mturquette@linaro.org>2014-02-27 00:23:29 +0400
commit5585f7317573873f95c1bb7748322c62a6c3a919 (patch)
tree91c8230f367233a21a4cdb61c72bbb94a5e27e5a /drivers/clk
parent2c97ec58420d852f3f0ede905b92fbab1df5961c (diff)
downloadlinux-5585f7317573873f95c1bb7748322c62a6c3a919.tar.xz
clk: socfpga: Fix integer overflow in clock calculation
Use 64-bit integer for calculating clock rate. Also use do_div for the 64-bit division. Signed-off-by: Graham Moore <grmoore@altera.com> Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/socfpga/clk-pll.c8
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/clk/socfpga/clk-pll.c b/drivers/clk/socfpga/clk-pll.c
index 362004e1e6fe..834b6e961971 100644
--- a/drivers/clk/socfpga/clk-pll.c
+++ b/drivers/clk/socfpga/clk-pll.c
@@ -44,7 +44,8 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
unsigned long parent_rate)
{
struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
- unsigned long divf, divq, vco_freq, reg;
+ unsigned long divf, divq, reg;
+ unsigned long long vco_freq;
unsigned long bypass;
reg = readl(socfpgaclk->hw.reg);
@@ -54,8 +55,9 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT;
divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT;
- vco_freq = parent_rate * (divf + 1);
- return vco_freq / (1 + divq);
+ vco_freq = (unsigned long long)parent_rate * (divf + 1);
+ do_div(vco_freq, (1 + divq));
+ return (unsigned long)vco_freq;
}
static struct clk_ops clk_pll_ops = {