diff options
| author | Oleksij Rempel <o.rempel@pengutronix.de> | 2023-01-31 11:46:25 +0300 |
|---|---|---|
| committer | Abel Vesa <abel.vesa@linaro.org> | 2023-01-31 15:45:03 +0300 |
| commit | 8bb289bb48b3e2966e8e165a4b9dcbba09573aa9 (patch) | |
| tree | 507cfc41f9eab006c2fb859d79f6958942cb1b9a /drivers/clk | |
| parent | ee394f636ad3cf0793042db049796147f708d483 (diff) | |
| download | linux-8bb289bb48b3e2966e8e165a4b9dcbba09573aa9.tar.xz | |
clk: imx6q: add ethernet refclock mux support
Add ethernet refclock mux support and set it to internal clock by
default. This configuration will not affect existing boards since
machine code currently overwrites this default.
The machine code will be fixed in a separate patch.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230131084642.709385-3-o.rempel@pengutronix.de
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/imx/clk-imx6q.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index da71e064531e..bf4c1d9c9928 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -12,6 +12,7 @@ #include <linux/clk-provider.h> #include <linux/err.h> #include <linux/io.h> +#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_irq.h> @@ -115,6 +116,10 @@ static struct clk_div_table video_div_table[] = { { /* sentinel */ } }; +static const char * enet_ref_sels[] = { "enet_ref", "enet_ref_pad", }; +static const u32 enet_ref_sels_table[] = { IMX6Q_GPR1_ENET_CLK_SEL_ANATOP, IMX6Q_GPR1_ENET_CLK_SEL_PAD }; +static const u32 enet_ref_sels_table_mask = IMX6Q_GPR1_ENET_CLK_SEL_ANATOP; + static unsigned int share_count_esai; static unsigned int share_count_asrc; static unsigned int share_count_ssi1; @@ -908,6 +913,12 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) hws[IMX6QDL_CLK_GPT_3M] = hws[IMX6QDL_CLK_GPT_IPG_PER]; + hws[IMX6QDL_CLK_ENET_REF_PAD] = imx6q_obtain_fixed_clk_hw(ccm_node, "enet_ref_pad", 0); + + hws[IMX6QDL_CLK_ENET_REF_SEL] = imx_clk_gpr_mux("enet_ref_sel", "fsl,imx6q-iomuxc-gpr", + IOMUXC_GPR1, enet_ref_sels, ARRAY_SIZE(enet_ref_sels), + enet_ref_sels_table, enet_ref_sels_table_mask); + imx_check_clk_hws(hws, IMX6QDL_CLK_END); of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); @@ -974,6 +985,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk); } + clk_set_parent(hws[IMX6QDL_CLK_ENET_REF_SEL]->clk, hws[IMX6QDL_CLK_ENET_REF]->clk); + imx_register_uart_clocks(); } CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init); |