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authorYoshinori Sato <ysato@users.sourceforge.jp>2015-05-31 17:25:35 +0300
committerYoshinori Sato <ysato@users.sourceforge.jp>2015-11-08 16:44:37 +0300
commitaca2518064556ae5658974d78cb71f4883911d3d (patch)
treeef2aa4a50b2129dbd07e9678b40b4960df88c979 /drivers/clk
parent7379047d5585187d1288486d4627873170d0005a (diff)
downloadlinux-aca2518064556ae5658974d78cb71f4883911d3d.tar.xz
h8300: unaligned divcr register support.
DIVCR is unaligned long word. So we need adjustment for long word align. Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/h8300/clk-div.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/clk/h8300/clk-div.c b/drivers/clk/h8300/clk-div.c
index 1dd5d14d5dbe..d71d01157dbb 100644
--- a/drivers/clk/h8300/clk-div.c
+++ b/drivers/clk/h8300/clk-div.c
@@ -19,6 +19,7 @@ static void __init h8300_div_clk_setup(struct device_node *node)
const char *parent_name;
void __iomem *divcr = NULL;
int width;
+ int offset;
num_parents = of_clk_get_parent_count(node);
if (num_parents < 1) {
@@ -31,11 +32,14 @@ static void __init h8300_div_clk_setup(struct device_node *node)
pr_err("%s: failed to map divide register", clk_name);
goto error;
}
+ offset = (unsigned long)divcr & 3;
+ offset = (3 - offset) * 8;
+ divcr = (void *)((unsigned long)divcr & ~3);
parent_name = of_clk_get_parent_name(node, 0);
of_property_read_u32(node, "renesas,width", &width);
clk = clk_register_divider(NULL, clk_name, parent_name,
- CLK_SET_RATE_GATE, divcr, 0, width,
+ CLK_SET_RATE_GATE, divcr, offset, width,
CLK_DIVIDER_POWER_OF_TWO, &clklock);
if (!IS_ERR(clk)) {
of_clk_add_provider(node, of_clk_src_simple_get, clk);