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authorYuantian Tang <andy.tang@nxp.com>2019-04-22 12:15:09 +0300
committerStephen Boyd <sboyd@kernel.org>2019-04-25 21:22:46 +0300
commitcc61ab9ba2da6587d2b8acfa9d3cf3900456d3b6 (patch)
tree0d057a93a236c40d8d8256c062f31b56b15de628 /drivers/clk
parentf34b2c26fc7d120b26cb181b8d4115675ec58244 (diff)
downloadlinux-cc61ab9ba2da6587d2b8acfa9d3cf3900456d3b6.tar.xz
clk: qoriq: add more PLL divider clocks support
More PLL divider clocks are needed by clock consumer IP. So enlarge the PLL divider array to accommodate more divider clocks. Signed-off-by: Yuantian Tang <andy.tang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/clk-qoriq.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 1212a9be7e80..5e2b3ac2d1ef 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -34,6 +34,7 @@
#define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */
#define CGB_PLL1 4
#define CGB_PLL2 5
+#define MAX_PLL_DIV 16
struct clockgen_pll_div {
struct clk *clk;
@@ -41,7 +42,7 @@ struct clockgen_pll_div {
};
struct clockgen_pll {
- struct clockgen_pll_div div[8];
+ struct clockgen_pll_div div[MAX_PLL_DIV];
};
#define CLKSEL_VALID 1
@@ -1128,7 +1129,7 @@ static void __init create_one_pll(struct clockgen *cg, int idx)
int ret;
/*
- * For platform PLL, there are 8 divider clocks.
+ * For platform PLL, there are MAX_PLL_DIV divider clocks.
* For core PLL, there are 4 divider clocks at most.
*/
if (idx != PLATFORM_PLL && i >= 4)