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authorChris Brandt <chris.brandt@renesas.com>2017-02-14 19:08:05 +0300
committerStephen Boyd <sboyd@codeaurora.org>2017-02-16 21:36:05 +0300
commitf59de563358eb9351b7f8f0ba2d3be2ebb70b93d (patch)
tree0e008be6cd260a00e1d49f024345af0a1d4abfa9 /drivers/clk
parent6ff8ec98e12f984b9d62e43f83b0a3c44e2bdc12 (diff)
downloadlinux-f59de563358eb9351b7f8f0ba2d3be2ebb70b93d.tar.xz
clk: renesas: mstp: ensure register writes complete
When there is no status bit, it is possible for the clock enable/disable operation to have not completed by the time the driver code resumes execution. This is due to the fact that write operations are sometimes queued and delayed internally. Doing a read ensures the write operations has completed. Fixes: b6face404f38 ("ARM: shmobile: r7s72100: add essential clock nodes to dtsi") Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/renesas/clk-mstp.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/renesas/clk-mstp.c b/drivers/clk/renesas/clk-mstp.c
index 3ce819c26077..4067216bf31f 100644
--- a/drivers/clk/renesas/clk-mstp.c
+++ b/drivers/clk/renesas/clk-mstp.c
@@ -91,6 +91,12 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
value |= bitmask;
cpg_mstp_write(group, value, group->smstpcr);
+ if (!group->mstpsr) {
+ /* dummy read to ensure write has completed */
+ cpg_mstp_read(group, group->smstpcr);
+ barrier_data(group->smstpcr);
+ }
+
spin_unlock_irqrestore(&group->lock, flags);
if (!enable || !group->mstpsr)