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authorAnup Patel <anup.patel@wdc.com>2020-08-17 15:42:50 +0300
committerPalmer Dabbelt <palmerdabbelt@google.com>2020-08-20 20:58:13 +0300
commit2bc3fc877aa9c4c8b80cc49f66dfcb7e4857a128 (patch)
tree0bee46a80c0d3d86a344e45c5fe1ef670e2f08b6 /drivers/clocksource/Kconfig
parent2ac6795fcc085e8d03649f1bbd0d70aaff612cad (diff)
downloadlinux-2bc3fc877aa9c4c8b80cc49f66dfcb7e4857a128.tar.xz
RISC-V: Remove CLINT related code from timer and arch
Right now the RISC-V timer driver is convoluted to support: 1. Linux RISC-V S-mode (with MMU) where it will use TIME CSR for clocksource and SBI timer calls for clockevent device. 2. Linux RISC-V M-mode (without MMU) where it will use CLINT MMIO counter register for clocksource and CLINT MMIO compare register for clockevent device. We now have a separate CLINT timer driver which also provide CLINT based IPI operations so let's remove CLINT MMIO related code from arch/riscv directory and RISC-V timer driver. Signed-off-by: Anup Patel <anup.patel@wdc.com> Tested-by: Emil Renner Berhing <kernel@esmil.dk> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'drivers/clocksource/Kconfig')
-rw-r--r--drivers/clocksource/Kconfig3
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index d95cc7234a66..68b087bff59c 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -653,9 +653,8 @@ config ATCPIT100_TIMER
This option enables support for the Andestech ATCPIT100 timers.
config RISCV_TIMER
- bool "Timer for the RISC-V platform"
+ bool "Timer for the RISC-V platform" if COMPILE_TEST
depends on GENERIC_SCHED_CLOCK && RISCV
- default y
select TIMER_PROBE
select TIMER_OF
help