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authorSrinivas Pandruvada <srinivas.pandruvada@linux.intel.com>2021-11-04 13:22:30 +0300
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2021-11-04 21:48:47 +0300
commit074d0cdfbb2f5985c5748fe80f6f8a2a7db8b63f (patch)
tree8c5ed1eeea9150ec9d3488d477f9d200d55e04c4 /drivers/cpufreq
parent5521055670a53bd495676d1163b40ecb0a37af9c (diff)
downloadlinux-074d0cdfbb2f5985c5748fe80f6f8a2a7db8b63f.tar.xz
cpufreq: intel_pstate: Clear HWP Status during HWP Interrupt enable
It is possible that some performance excursions happened before OS boot or enable HWP interrupts. So clear MSR_HWP_STATUS bits when we enable HWP interrupt. In this way a next excursion will results in a HWP interrupt. The status bits of MSR_HWP_STATUS must be cleared (0) by software so that a new status condition change will cause the hardware to set the bit again and issue the notification. Fixes: 57577c996d73 ("cpufreq: intel_pstate: Process HWP Guaranteed change notification") Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'drivers/cpufreq')
-rw-r--r--drivers/cpufreq/intel_pstate.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c
index 2bb847650b9d..815df3daae9d 100644
--- a/drivers/cpufreq/intel_pstate.c
+++ b/drivers/cpufreq/intel_pstate.c
@@ -1652,6 +1652,7 @@ static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata)
/* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x01);
+ wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
}
}