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| author | Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> | 2022-02-22 16:09:03 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2022-03-29 20:17:49 +0300 |
| commit | a6aa462c3efc144808b0cf8a0fe993d4fe2c079a (patch) | |
| tree | 9e4ac23aa71109930d0a79d3475f72064b0bea65 /drivers/cpuidle | |
| parent | d583804c97c5ae7a7eba9c44982adcb106c2d160 (diff) | |
| download | linux-a6aa462c3efc144808b0cf8a0fe993d4fe2c079a.tar.xz | |
clk: zynq: Update the parameters to zynq_clk_register_periph_clk
In case there are only one gate or the two_gate is 0 the clk1 clock
passed is not used. We are passing 0 which is arm_pll.
Pass a invalid clock instead.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Link: https://lore.kernel.org/r/20220222130903.17235-3-shubhrajyoti.datta@xilinx.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/cpuidle')
0 files changed, 0 insertions, 0 deletions