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authorCyrille Pitchen <cyrille.pitchen@atmel.com>2016-10-03 15:33:16 +0300
committerHerbert Xu <herbert@gondor.apana.org.au>2016-10-21 06:03:39 +0300
commitd52db5188a87dcdf8e5bf024f45543b362a1a85f (patch)
treeb11af2064e8b640cd8307d004361bc298a16bfb6 /drivers/crypto/atmel-aes-regs.h
parentf709dc86bc4f9d8c320ceb9a12ac304756129dd5 (diff)
downloadlinux-d52db5188a87dcdf8e5bf024f45543b362a1a85f.tar.xz
crypto: atmel-aes - add support to the XTS mode
This patch adds the xts(aes) algorithm, which is supported from hardware version 0x500 and above (sama5d2x). Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto/atmel-aes-regs.h')
-rw-r--r--drivers/crypto/atmel-aes-regs.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/crypto/atmel-aes-regs.h b/drivers/crypto/atmel-aes-regs.h
index 6c2951bb70b1..0ec04407b533 100644
--- a/drivers/crypto/atmel-aes-regs.h
+++ b/drivers/crypto/atmel-aes-regs.h
@@ -28,6 +28,7 @@
#define AES_MR_OPMOD_CFB (0x3 << 12)
#define AES_MR_OPMOD_CTR (0x4 << 12)
#define AES_MR_OPMOD_GCM (0x5 << 12)
+#define AES_MR_OPMOD_XTS (0x6 << 12)
#define AES_MR_LOD (0x1 << 15)
#define AES_MR_CFBS_MASK (0x7 << 16)
#define AES_MR_CFBS_128b (0x0 << 16)
@@ -67,6 +68,9 @@
#define AES_CTRR 0x98
#define AES_GCMHR(x) (0x9c + ((x) * 0x04))
+#define AES_TWR(x) (0xc0 + ((x) * 0x04))
+#define AES_ALPHAR(x) (0xd0 + ((x) * 0x04))
+
#define AES_HW_VERSION 0xFC
#endif /* __ATMEL_AES_REGS_H__ */