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| author | Harsh Jain <harsh@chelsio.com> | 2017-06-15 10:13:43 +0300 |
|---|---|---|
| committer | Herbert Xu <herbert@gondor.apana.org.au> | 2017-06-20 06:21:35 +0300 |
| commit | b8fd1f4170e7e8bda45d7bcc750e909c859ec714 (patch) | |
| tree | ed3805bce0ae00492bc44acafea3f3fa24516584 /drivers/crypto/chelsio/chcr_core.c | |
| parent | d600fc8aae746de71631b52ff40d02cf90dd3b74 (diff) | |
| download | linux-b8fd1f4170e7e8bda45d7bcc750e909c859ec714.tar.xz | |
crypto: chcr - Add ctr mode and process large sg entries for cipher
It send multiple WRs to H/W to handle large sg lists. Adds ctr(aes)
and rfc(ctr(aes)) modes.
Signed-off-by: Harsh Jain <harsh@chelsio.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto/chelsio/chcr_core.c')
| -rw-r--r-- | drivers/crypto/chelsio/chcr_core.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/drivers/crypto/chelsio/chcr_core.c b/drivers/crypto/chelsio/chcr_core.c index c28e018e0773..a6c938a913c7 100644 --- a/drivers/crypto/chelsio/chcr_core.c +++ b/drivers/crypto/chelsio/chcr_core.c @@ -115,7 +115,6 @@ static int cpl_fw6_pld_handler(struct chcr_dev *dev, /* call completion callback with failure status */ if (req) { error_status = chcr_handle_resp(req, input, error_status); - req->complete(req, error_status); } else { pr_err("Incorrect request address from the firmware\n"); return -EFAULT; |