diff options
| author | Marco Chiappero <marco.chiappero@intel.com> | 2022-04-07 19:54:42 +0300 |
|---|---|---|
| committer | Herbert Xu <herbert@gondor.apana.org.au> | 2022-04-15 11:34:26 +0300 |
| commit | 9ff9139b5ddbd4d3ea93558a2d477a6bab4eff94 (patch) | |
| tree | f96ae90ff3cc7b19a8fcd654318713d85670ef4f /drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.h | |
| parent | 0eaa51543273fd0f4ba9bea83638f7033436e5eb (diff) | |
| download | linux-9ff9139b5ddbd4d3ea93558a2d477a6bab4eff94.tar.xz | |
crypto: qat - fix ETR sources enabled by default on GEN2 devices
When the driver starts the device, it enables all the necessary
interrupts. However interrupts associated to host rings are enabled by
default on all GEN2 devices (except for dh895x) even when SR-IOV is
active. Fix this behaviour by checking if data structures associated to
VFs have been allocated to determine whether to enable such interrupts
or not.
Since the logic for the fix is the same across GEN2 devices, replace
the function to be fixed (adf_enable_ints()) with a single one
(adf_gen2_enable_ints()) in the common GEN2 code in adf_gen2_hw_data.c.
Likewise, remove the unnecessary duplication of defines too.
Signed-off-by: Marco Chiappero <marco.chiappero@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.h')
| -rw-r--r-- | drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.h | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.h b/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.h index 1b86f828725c..336a06f11dbd 100644 --- a/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.h +++ b/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.h @@ -13,10 +13,6 @@ #define ADF_C3XXX_ACCELERATORS_MASK 0x7 #define ADF_C3XXX_ACCELENGINES_MASK 0x3F #define ADF_C3XXX_ETR_MAX_BANKS 16 -#define ADF_C3XXX_SMIAPF0_MASK_OFFSET (0x3A000 + 0x28) -#define ADF_C3XXX_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30) -#define ADF_C3XXX_SMIA0_MASK 0xFFFF -#define ADF_C3XXX_SMIA1_MASK 0x1 #define ADF_C3XXX_SOFTSTRAP_CSR_OFFSET 0x2EC /* AE to function mapping */ |