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authorMarco Chiappero <marco.chiappero@intel.com>2021-11-17 17:30:48 +0300
committerHerbert Xu <herbert@gondor.apana.org.au>2021-11-26 08:20:47 +0300
commit9baf2de7ee4eeaca5cf95d1a399182ab83aa42b8 (patch)
treee9d286b04e18305ea1843a14d3297e993df51056 /drivers/crypto/qat/qat_common/adf_accel_devices.h
parentbc63dabe525402b91320192ff1758f0d05b159c6 (diff)
downloadlinux-9baf2de7ee4eeaca5cf95d1a399182ab83aa42b8.tar.xz
crypto: qat - differentiate between pf2vf and vf2pf offset
Add the function get_vf2pf_offset() to adf_pfvf_ops to differentiate the CSRs used for pf2vf and vf2pf. Offsets may or may not be direction specific depending on QAT generation. Since in QAT GEN2 the CSR is not direction specific, i.e. there is a single mailbox register shared for pf2vf and vf2pf, both get_vf2pf_offset() and get_vf2pf_offset() will return the same offset. This change is to make the direction explicit, so it is easier to understand and debug and also in preparation for the introduction of PFVF support in the qat_4xxx driver since QAT GEN4 devices have a separate CSR for pf2vf and vf2pf communications. Signed-off-by: Marco Chiappero <marco.chiappero@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto/qat/qat_common/adf_accel_devices.h')
-rw-r--r--drivers/crypto/qat/qat_common/adf_accel_devices.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/crypto/qat/qat_common/adf_accel_devices.h b/drivers/crypto/qat/qat_common/adf_accel_devices.h
index a1baa65bd034..d9b2cc935b61 100644
--- a/drivers/crypto/qat/qat_common/adf_accel_devices.h
+++ b/drivers/crypto/qat/qat_common/adf_accel_devices.h
@@ -150,6 +150,7 @@ struct adf_etr_ring_data;
struct adf_pfvf_ops {
int (*enable_comms)(struct adf_accel_dev *accel_dev);
u32 (*get_pf2vf_offset)(u32 i);
+ u32 (*get_vf2pf_offset)(u32 i);
u32 (*get_vf2pf_sources)(void __iomem *pmisc_addr);
void (*enable_vf2pf_interrupts)(void __iomem *pmisc_addr, u32 vf_mask);
void (*disable_vf2pf_interrupts)(void __iomem *pmisc_addr, u32 vf_mask);