diff options
| author | Marco Chiappero <marco.chiappero@intel.com> | 2021-12-16 12:13:32 +0300 |
|---|---|---|
| committer | Herbert Xu <herbert@gondor.apana.org.au> | 2021-12-24 06:18:27 +0300 |
| commit | 0bba03ce9739be004d7e7060a1a127418fd0055c (patch) | |
| tree | b0b46d08dbee15948d0f5d01beca0f74ec6e867f /drivers/crypto/qat/qat_common/adf_pfvf_msg.h | |
| parent | a9dc0d966605377e9aa512efdcaf9653f40cc2d5 (diff) | |
| download | linux-0bba03ce9739be004d7e7060a1a127418fd0055c.tar.xz | |
crypto: qat - add PFVF support to enable the reset of ring pairs
Extend support for resetting ring pairs on the device to VFs. Such
reset happens by sending a request to the PF over the PFVF protocol.
This patch defines two new PFVF messages and adds the PFVF logic for
handling the request on PF, triggering the reset, and VFs, accepting the
'success'/'error' response.
This feature is GEN4 specific.
This patch is based on earlier work done by Zelin Deng.
Signed-off-by: Marco Chiappero <marco.chiappero@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Reviewed-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto/qat/qat_common/adf_pfvf_msg.h')
| -rw-r--r-- | drivers/crypto/qat/qat_common/adf_pfvf_msg.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/crypto/qat/qat_common/adf_pfvf_msg.h b/drivers/crypto/qat/qat_common/adf_pfvf_msg.h index f00e9e2c585b..86b0e7baa4d3 100644 --- a/drivers/crypto/qat/qat_common/adf_pfvf_msg.h +++ b/drivers/crypto/qat/qat_common/adf_pfvf_msg.h @@ -99,6 +99,8 @@ enum pf2vf_msgtype { ADF_PF2VF_MSGTYPE_RESTARTING = 0x01, ADF_PF2VF_MSGTYPE_VERSION_RESP = 0x02, ADF_PF2VF_MSGTYPE_BLKMSG_RESP = 0x03, +/* Values from 0x10 are Gen4 specific, message type is only 4 bits in Gen2 devices. */ + ADF_PF2VF_MSGTYPE_RP_RESET_RESP = 0x10, }; /* VF->PF messages */ @@ -110,6 +112,8 @@ enum vf2pf_msgtype { ADF_VF2PF_MSGTYPE_LARGE_BLOCK_REQ = 0x07, ADF_VF2PF_MSGTYPE_MEDIUM_BLOCK_REQ = 0x08, ADF_VF2PF_MSGTYPE_SMALL_BLOCK_REQ = 0x09, +/* Values from 0x10 are Gen4 specific, message type is only 4 bits in Gen2 devices. */ + ADF_VF2PF_MSGTYPE_RP_RESET = 0x10, }; /* VF/PF compatibility version. */ @@ -134,6 +138,16 @@ enum pf2vf_compat_response { ADF_PF2VF_VF_COMPAT_UNKNOWN = 0x03, }; +enum ring_reset_result { + RPRESET_SUCCESS = 0x01, + RPRESET_NOT_SUPPORTED = 0x02, + RPRESET_INVAL_BANK = 0x03, + RPRESET_TIMEOUT = 0x04, +}; + +#define ADF_VF2PF_RNG_RESET_RP_MASK GENMASK(1, 0) +#define ADF_VF2PF_RNG_RESET_RSVD_MASK GENMASK(25, 2) + /* PF->VF Block Responses */ #define ADF_PF2VF_BLKMSG_RESP_TYPE_MASK GENMASK(1, 0) #define ADF_PF2VF_BLKMSG_RESP_DATA_MASK GENMASK(9, 2) |