diff options
| author | Marco Chiappero <marco.chiappero@intel.com> | 2021-12-16 12:13:31 +0300 |
|---|---|---|
| committer | Herbert Xu <herbert@gondor.apana.org.au> | 2021-12-24 06:18:27 +0300 |
| commit | a9dc0d966605377e9aa512efdcaf9653f40cc2d5 (patch) | |
| tree | f0cc0817a1ea811e6ccd083f8d78a4b8a664b4dd /drivers/crypto/qat/qat_common/adf_pfvf_msg.h | |
| parent | 925b3069cf6e37a86fc752a35578ec875772bc7c (diff) | |
| download | linux-a9dc0d966605377e9aa512efdcaf9653f40cc2d5.tar.xz | |
crypto: qat - add PFVF support to the GEN4 host driver
So far PFVF support for GEN4 devices has been kept effectively disabled
due to lack of support. This patch adds all the GEN4 specific logic to
make PFVF fully functional on PF.
Signed-off-by: Marco Chiappero <marco.chiappero@intel.com>
Co-developed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Reviewed-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto/qat/qat_common/adf_pfvf_msg.h')
| -rw-r--r-- | drivers/crypto/qat/qat_common/adf_pfvf_msg.h | 29 |
1 files changed, 28 insertions, 1 deletions
diff --git a/drivers/crypto/qat/qat_common/adf_pfvf_msg.h b/drivers/crypto/qat/qat_common/adf_pfvf_msg.h index 1d3cad7d4999..f00e9e2c585b 100644 --- a/drivers/crypto/qat/qat_common/adf_pfvf_msg.h +++ b/drivers/crypto/qat/qat_common/adf_pfvf_msg.h @@ -6,7 +6,8 @@ #include <linux/bits.h> /* - * PF<->VF Messaging + * PF<->VF Gen2 Messaging format + * * The PF has an array of 32-bit PF2VF registers, one for each VF. The * PF can access all these registers; each VF can access only the one * register associated with that particular VF. @@ -53,6 +54,32 @@ * respectively, the other 16 bits are written to first with a defined * IN_USE_BY pattern as part of a collision control scheme (see function * adf_gen2_pfvf_send() in adf_pf2vf_msg.c). + * + * + * PF<->VF Gen4 Messaging format + * + * Similarly to the gen2 messaging format, 32-bit long registers are used for + * communication between PF and VFs. However, each VF and PF share a pair of + * 32-bits register to avoid collisions: one for PV to VF messages and one + * for VF to PF messages. + * + * Both the Interrupt bit and the Message Origin bit retain the same position + * and meaning, although non-system messages are now deprecated and not + * expected. + * + * 31 30 9 8 7 6 5 4 3 2 1 0 + * _______________________________________________ + * | | | . . . | | | | | | | | | | | + * +-----------------------------------------------+ + * \_____________________/ \_______________/ ^ ^ + * ^ ^ | | + * | | | PF/VF Int + * | | Message Origin + * | Message Type + * Message-specific Data/Reserved + * + * For both formats, the message reception is acknowledged by lowering the + * interrupt bit on the register where the message was sent. */ /* PFVF message common bits */ |