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| author | Dan Williams <dan.j.williams@intel.com> | 2021-06-16 02:18:17 +0300 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2021-06-16 02:47:14 +0300 |
| commit | 8fdcb1704f61a8fd9be0f3849a174d084def0666 (patch) | |
| tree | 716bb7930778e4b62c604b7a8c39801acca342b1 /drivers/cxl/Kconfig | |
| parent | 6af7139c979474a29a6ad642c9bf32d92e24c5bc (diff) | |
| download | linux-8fdcb1704f61a8fd9be0f3849a174d084def0666.tar.xz | |
cxl/pmem: Add initial infrastructure for pmem support
Register an 'nvdimm-bridge' device to act as an anchor for a libnvdimm
bus hierarchy. Also, flesh out the cxl_bus definition to allow a
cxl_nvdimm_bridge_driver to attach to the bridge and trigger the
nvdimm-bus registration.
The creation of the bridge is gated on the detection of a PMEM capable
address space registered to the root. The bridge indirection allows the
libnvdimm module to remain unloaded on platforms without PMEM support.
Given that the probing of ACPI0017 is asynchronous to CXL endpoint
devices, and the expectation that CXL endpoint devices register other
PMEM resources on the 'CXL' nvdimm bus, a workqueue is added. The
workqueue is needed to run bus_rescan_devices() outside of the
device_lock() of the nvdimm-bridge device to rendezvous nvdimm resources
as they arrive. For now only the bus is taken online/offline in the
workqueue.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/162379909706.2993820.14051258608641140169.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl/Kconfig')
| -rw-r--r-- | drivers/cxl/Kconfig | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig index 1a44b173dcbc..e6de221cc568 100644 --- a/drivers/cxl/Kconfig +++ b/drivers/cxl/Kconfig @@ -62,4 +62,17 @@ config CXL_ACPI Memory regions to be managed by LIBNVDIMM. If unsure say 'm'. + +config CXL_PMEM + tristate "CXL PMEM: Persistent Memory Support" + depends on LIBNVDIMM + default CXL_BUS + help + In addition to typical memory resources a platform may also advertise + support for persistent memory attached via CXL. This support is + managed via a bridge driver from CXL to the LIBNVDIMM system + subsystem. Say 'y/m' to enable support for enumerating and + provisioning the persistent memory capacity of CXL memory expanders. + + If unsure say 'm'. endif |