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author | Dan Williams <dan.j.williams@intel.com> | 2022-05-27 10:56:59 +0300 |
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committer | Dan Williams <dan.j.williams@intel.com> | 2022-07-22 03:19:24 +0300 |
commit | de516b40116e98c60ee475e92108453686098c85 (patch) | |
tree | b9ad5e5e6ac81f9648b26cc52e37003a54d17ed0 /drivers/cxl/acpi.c | |
parent | cf880423b6a0599499c1f83542cab0b75daa29ba (diff) | |
download | linux-de516b40116e98c60ee475e92108453686098c85.tar.xz |
cxl/port: Record dport in endpoint references
Recall that the primary role of the cxl_mem driver is to probe if the
given endpoint is connected to a CXL port topology. In that process it
walks its device ancestry to its PCI root port. If that root port is
also a CXL root port then the probe process adds cxl_port object
instances at switch in the path between to the root and the endpoint. As
those cxl_port instances are added, or if a previous enumeration
attempt already created the port, a 'struct cxl_ep' instance is
registered with that port to track the endpoints interested in that
port.
At the time the cxl_ep is registered the downstream egress path from the
port to the endpoint is known. Take the opportunity to record that
information as it will be needed for dynamic programming of decoder
targets during region provisioning.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/165784329944.1758207.15203961796832072116.stgit@dwillia2-xfh.jf.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl/acpi.c')
0 files changed, 0 insertions, 0 deletions