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| author | Dan Williams <dan.j.williams@intel.com> | 2022-05-23 22:15:35 +0300 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-07-22 03:19:23 +0300 |
| commit | 2c8669033f16f5d791e10a5bdd42e39c7380da57 (patch) | |
| tree | 56607c894bdaf54da1f0d7a197263f8879e33a8e /drivers/cxl/core/hdm.c | |
| parent | 9c57cde0dcbd0f76f649d152b83a2b9316277b22 (diff) | |
| download | linux-2c8669033f16f5d791e10a5bdd42e39c7380da57.tar.xz | |
cxl/hdm: Add 'mode' attribute to decoder objects
Recall that the Device Physical Address (DPA) space of a CXL Memory
Expander is potentially partitioned into a volatile and persistent
portion. A decoder maps a Host Physical Address (HPA) range to a DPA
range and that translation depends on the value of all previous (lower
instance number) decoders before the current one.
In preparation for allowing dynamic provisioning of regions, decoders
need an ABI to indicate which DPA partition a decoder targets. This ABI
needs to be prepared for the possibility that some other agent committed
and locked a decoder that spans the partition boundary.
Add 'decoderX.Y/mode' to endpoint decoders that indicates which
partition 'ram' / 'pmem' the decoder targets, or 'mixed' if the decoder
currently spans the partition boundary.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/165603881967.551046.6007594190951596439.stgit@dwillia2-xfh
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl/core/hdm.c')
| -rw-r--r-- | drivers/cxl/core/hdm.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c index 47e3af440b3d..c2cff5783fda 100644 --- a/drivers/cxl/core/hdm.c +++ b/drivers/cxl/core/hdm.c @@ -226,6 +226,16 @@ static int __cxl_dpa_reserve(struct cxl_endpoint_decoder *cxled, cxled->dpa_res = res; cxled->skip = skipped; + if (resource_contains(&cxlds->pmem_res, res)) + cxled->mode = CXL_DECODER_PMEM; + else if (resource_contains(&cxlds->ram_res, res)) + cxled->mode = CXL_DECODER_RAM; + else { + dev_dbg(dev, "decoder%d.%d: %pr mixed\n", port->id, + cxled->cxld.id, cxled->dpa_res); + cxled->mode = CXL_DECODER_MIXED; + } + return 0; } |