diff options
| author | Dan Williams <dan.j.williams@intel.com> | 2022-11-29 20:48:42 +0300 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-12-04 00:40:17 +0300 |
| commit | a1554e9cac5ea04aaf2fb2de0df9936a94cb96fc (patch) | |
| tree | cff52081d64406c4ffa914c7eddad07843d7aa2c /drivers/cxl/core/hdm.c | |
| parent | 920d8d2c60787bf63e023b120e81ca788d4191ff (diff) | |
| download | linux-a1554e9cac5ea04aaf2fb2de0df9936a94cb96fc.tar.xz | |
cxl/pci: Prepare for mapping RAS Capability Structure
The RAS Capabilitiy Structure is a CXL Component register capability
block. Unlike the HDM Decoder Capability, it will be referenced by the
cxl_pci driver in response to PCIe AER events. Due to this it is no
longer the case that cxl_map_component_regs() can assume that it should
map all component registers. Plumb a bitmask of capability ids to map
through cxl_map_component_regs().
For symmetry cxl_probe_device_regs() is updated to populate @id in
'struct cxl_reg_map' even though cxl_map_device_regs() does not have a
need to map a subset of the device registers per caller.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/166974412214.1608150.11487843455070795378.stgit@djiang5-desk3.ch.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl/core/hdm.c')
| -rw-r--r-- | drivers/cxl/core/hdm.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c index 061551148cfe..100d0881bde4 100644 --- a/drivers/cxl/core/hdm.c +++ b/drivers/cxl/core/hdm.c @@ -97,7 +97,8 @@ static int map_hdm_decoder_regs(struct cxl_port *port, void __iomem *crb, return -ENXIO; } - return cxl_map_component_regs(&port->dev, regs, &map); + return cxl_map_component_regs(&port->dev, regs, &map, + BIT(CXL_CM_CAP_CAP_ID_HDM)); } /** |