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| author | Robert Richter <rrichter@amd.com> | 2023-06-22 23:55:11 +0300 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2023-06-25 22:22:53 +0300 |
| commit | 5d2ffbe4b81a3b6353bf888a523e7e5d4fec47ad (patch) | |
| tree | 536b1713da2cbbd90882e2d75a93de5cb97fda0c /drivers/cxl/cxl.h | |
| parent | 19ab69a60e3ba58b4942b9ab5095cf90477a54ce (diff) | |
| download | linux-5d2ffbe4b81a3b6353bf888a523e7e5d4fec47ad.tar.xz | |
cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport
Same as for ports, also store the downstream port's Component Register
mappings, use struct cxl_dport for that.
Signed-off-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20230622205523.85375-16-terry.bowman@amd.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl/cxl.h')
| -rw-r--r-- | drivers/cxl/cxl.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 37fa5b565362..b1adca9b27ba 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -595,6 +595,7 @@ struct cxl_rcrb_info { /** * struct cxl_dport - CXL downstream port * @dport_dev: PCI bridge or firmware device representing the downstream link + * @comp_map: component register capability mappings * @port_id: unique hardware identifier for dport in decoder target list * @rcrb: Data about the Root Complex Register Block layout * @rch: Indicate whether this dport was enumerated in RCH or VH mode @@ -602,6 +603,7 @@ struct cxl_rcrb_info { */ struct cxl_dport { struct device *dport_dev; + struct cxl_register_map comp_map; int port_id; struct cxl_rcrb_info rcrb; bool rch; |