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| author | Dan Williams <dan.j.williams@intel.com> | 2023-06-15 22:53:40 +0300 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2023-06-26 00:32:18 +0300 |
| commit | 8f0220af58c3b73e9041377a23708d37600b33c1 (patch) | |
| tree | 33eaab177f2e894717136667dbcee0ac46e26185 /drivers/cxl/cxl.h | |
| parent | 516b300c4ca86aa7953b75ce79b5c5eea5779b22 (diff) | |
| download | linux-8f0220af58c3b73e9041377a23708d37600b33c1.tar.xz | |
Revert "cxl/port: Enable the HDM decoder capability for switch ports"
commit eb0764b822b9 ("cxl/port: Enable the HDM decoder capability for switch ports")
...was added on the observation of CXL memory not being accessible after
setting up a region on a "cold-plugged" device. A "cold-plugged" CXL
device is one that was not present at boot, so platform-firmware/BIOS
has no chance to set it up.
While it is true that the debug found the enable bit clear in the
host-bridge's instance of the global control register (CXL 3.0
8.2.4.19.2 CXL HDM Decoder Global Control Register), that bit is
described as:
"This bit is only applicable to CXL.mem devices and shall
return 0 on CXL Host Bridges and Upstream Switch Ports."
So it is meant to be zero, and further testing confirmed that this "fix"
had no effect on the failure. Revert it, and be more vigilant about
proposed fixes in the future. Since the original copied stable@, flag
this revert for stable@ as well.
Cc: <stable@vger.kernel.org>
Fixes: eb0764b822b9 ("cxl/port: Enable the HDM decoder capability for switch ports")
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/168685882012.3475336.16733084892658264991.stgit@dwillia2-xfh.jf.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl/cxl.h')
| -rw-r--r-- | drivers/cxl/cxl.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index f309b1387858..f0c428cb9a71 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -710,7 +710,6 @@ struct cxl_endpoint_dvsec_info { struct cxl_hdm; struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port, struct cxl_endpoint_dvsec_info *info); -int devm_cxl_enable_hdm(struct cxl_port *port, struct cxl_hdm *cxlhdm); int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm, struct cxl_endpoint_dvsec_info *info); int devm_cxl_add_passthrough_decoder(struct cxl_port *port); |