diff options
| author | Robert Richter <rrichter@amd.com> | 2023-06-22 23:55:07 +0300 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2023-06-25 21:51:36 +0300 |
| commit | f1d0525effc4fffe821905671ea24c30a4bfa393 (patch) | |
| tree | 476d2207ce182887cae01e8cb94cedd95b7efd1a /drivers/cxl/port.c | |
| parent | d8bffff2016f7aef1c1dbe01125720475507b6f2 (diff) | |
| download | linux-f1d0525effc4fffe821905671ea24c30a4bfa393.tar.xz | |
cxl/regs: Remove early capability checks in Component Register setup
When probing the Component Registers in function cxl_probe_regs()
there are also checks for the existence of the HDM and RAS
capabilities. The checks may fail for components that do not implement
the HDM capability causing the Component Registers setup to fail too.
Remove the checks for a generalized use of cxl_probe_regs() and check
them directly before mapping the RAS or HDM capabilities. This allows
it to setup other Component Registers esp. of an RCH Downstream Port,
which will be implemented in a follow-on patch.
Signed-off-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20230622205523.85375-12-terry.bowman@amd.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl/port.c')
| -rw-r--r-- | drivers/cxl/port.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index 4cef2bf45ad2..01e84ea54f56 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -102,8 +102,11 @@ static int cxl_endpoint_port_probe(struct cxl_port *port) return rc; cxlhdm = devm_cxl_setup_hdm(port, &info); - if (IS_ERR(cxlhdm)) + if (IS_ERR(cxlhdm)) { + if (PTR_ERR(cxlhdm) == -ENODEV) + dev_err(&port->dev, "HDM decoder registers not found\n"); return PTR_ERR(cxlhdm); + } /* Cache the data early to ensure is_visible() works */ read_cdat_data(port); |