diff options
author | Dave Jiang <dave.jiang@intel.com> | 2022-12-06 00:16:07 +0300 |
---|---|---|
committer | Dan Williams <dan.j.williams@intel.com> | 2022-12-06 05:17:16 +0300 |
commit | 83351ddb786b30952485a5c302cd0cffbd62097e (patch) | |
tree | 68c5691584d791bcc72b10fb8e12153544e89676 /drivers/cxl | |
parent | d3cdf4585f2f9122d1165acca40e801c75afa320 (diff) | |
download | linux-83351ddb786b30952485a5c302cd0cffbd62097e.tar.xz |
cxl: update names for interleave granularity conversion macros
Change names for granularity macros to clearly indicate which
variable is encoded and which is the actual granularity.
granularity == interleave granularity
eig == encoded interleave granularity
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/167027493237.3124429.8948852388671827664.stgit@djiang5-desk3.ch.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl')
-rw-r--r-- | drivers/cxl/acpi.c | 4 | ||||
-rw-r--r-- | drivers/cxl/core/hdm.c | 6 | ||||
-rw-r--r-- | drivers/cxl/core/region.c | 6 | ||||
-rw-r--r-- | drivers/cxl/cxl.h | 13 |
4 files changed, 15 insertions, 14 deletions
diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c index f495f3ce45d1..99522e1b3993 100644 --- a/drivers/cxl/acpi.c +++ b/drivers/cxl/acpi.c @@ -86,7 +86,7 @@ static int cxl_parse_cxims(union acpi_subtable_headers *header, void *arg, unsigned int hbig, nr_maps; int rc; - rc = cxl_to_granularity(cxims->hbig, &hbig); + rc = eig_to_granularity(cxims->hbig, &hbig); if (rc) return rc; @@ -224,7 +224,7 @@ static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg, rc = cxl_to_ways(cfmws->interleave_ways, &ways); if (rc) return rc; - rc = cxl_to_granularity(cfmws->granularity, &ig); + rc = eig_to_granularity(cfmws->granularity, &ig); if (rc) return rc; for (i = 0; i < ways; i++) diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c index 100d0881bde4..40b2ea99d92f 100644 --- a/drivers/cxl/core/hdm.c +++ b/drivers/cxl/core/hdm.c @@ -497,7 +497,7 @@ static void cxld_set_interleave(struct cxl_decoder *cxld, u32 *ctrl) if (WARN_ONCE(ways_to_cxl(cxld->interleave_ways, &eiw), "invalid interleave_ways: %d\n", cxld->interleave_ways)) return; - if (WARN_ONCE(granularity_to_cxl(cxld->interleave_granularity, &eig), + if (WARN_ONCE(granularity_to_eig(cxld->interleave_granularity, &eig), "invalid interleave_granularity: %d\n", cxld->interleave_granularity)) return; @@ -749,8 +749,8 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld, port->id, cxld->id, ctrl); return rc; } - rc = cxl_to_granularity(FIELD_GET(CXL_HDM_DECODER0_CTRL_IG_MASK, ctrl), - &cxld->interleave_granularity); + rc = eig_to_granularity(FIELD_GET(CXL_HDM_DECODER0_CTRL_IG_MASK, ctrl), + &cxld->interleave_granularity); if (rc) return rc; diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index c56ddfed3393..6f3ca5c6f9f3 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -391,7 +391,7 @@ static ssize_t interleave_granularity_store(struct device *dev, if (rc) return rc; - rc = granularity_to_cxl(val, &ig); + rc = granularity_to_eig(val, &ig); if (rc) return rc; @@ -1028,7 +1028,7 @@ static int cxl_port_setup_targets(struct cxl_port *port, parent_iw = parent_cxld->interleave_ways; } - rc = granularity_to_cxl(parent_ig, &peig); + rc = granularity_to_eig(parent_ig, &peig); if (rc) { dev_dbg(&cxlr->dev, "%s:%s: invalid parent granularity: %d\n", dev_name(parent_port->uport), @@ -1065,7 +1065,7 @@ static int cxl_port_setup_targets(struct cxl_port *port, eig = peig; } - rc = cxl_to_granularity(eig, &ig); + rc = eig_to_granularity(eig, &ig); if (rc) { dev_dbg(&cxlr->dev, "%s:%s: invalid interleave: %d\n", dev_name(port->uport), dev_name(&port->dev), diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index ed2b0a2e80e2..7d0c81172a58 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -74,11 +74,11 @@ static inline int cxl_hdm_decoder_count(u32 cap_hdr) } /* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */ -static inline int cxl_to_granularity(u16 ig, unsigned int *val) +static inline int eig_to_granularity(u16 eig, unsigned int *granularity) { - if (ig > CXL_DECODER_MAX_ENCODED_IG) + if (eig > CXL_DECODER_MAX_ENCODED_IG) return -EINVAL; - *val = CXL_DECODER_MIN_GRANULARITY << ig; + *granularity = CXL_DECODER_MIN_GRANULARITY << eig; return 0; } @@ -99,11 +99,12 @@ static inline int cxl_to_ways(u8 eniw, unsigned int *val) return 0; } -static inline int granularity_to_cxl(int g, u16 *ig) +static inline int granularity_to_eig(int granularity, u16 *eig) { - if (g > SZ_16K || g < CXL_DECODER_MIN_GRANULARITY || !is_power_of_2(g)) + if (granularity > SZ_16K || granularity < CXL_DECODER_MIN_GRANULARITY || + !is_power_of_2(granularity)) return -EINVAL; - *ig = ilog2(g) - 8; + *eig = ilog2(granularity) - 8; return 0; } |