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authorRobert Richter <rrichter@amd.com>2024-04-24 18:47:56 +0300
committerDave Jiang <dave.jiang@intel.com>2024-04-30 20:43:48 +0300
commit4cce9c6d4bde821c21f7bd75c26f1e98a00d3858 (patch)
tree3e05a40300eaf618cf5438c3c35ad1fcf1435ad3 /drivers/cxl
parent4afaed94bc2f635fa03ea1c2cdb9c5bf1ef9bd9b (diff)
downloadlinux-4cce9c6d4bde821c21f7bd75c26f1e98a00d3858.tar.xz
cxl: Fix use of phys_to_target_node() for x86
The CXL driver uses both functions phys_to_target_node() and memory_add_physaddr_to_nid(). The x86 architecture relies on the NUMA_KEEP_MEMINFO kernel option enabled for both functions to work correct. Update Kconfig to make sure the option is always enabled for the driver. Suggested-by: Dan Williams <dan.j.williams@intel.com> Link: http://lore.kernel.org/r/65f8b191c0422_aa222941b@dwillia2-mobl3.amr.corp.intel.com.notmuch Reviewed-by: Ira Weiny <ira.weiny@intel.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Robert Richter <rrichter@amd.com> Link: https://lore.kernel.org/r/20240424154756.2152614-1-rrichter@amd.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Diffstat (limited to 'drivers/cxl')
-rw-r--r--drivers/cxl/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig
index 5f3c9c5529b9..99b5c25be079 100644
--- a/drivers/cxl/Kconfig
+++ b/drivers/cxl/Kconfig
@@ -6,6 +6,7 @@ menuconfig CXL_BUS
select FW_UPLOAD
select PCI_DOE
select FIRMWARE_TABLE
+ select NUMA_KEEP_MEMINFO if (NUMA && X86)
help
CXL is a bus that is electrically compatible with PCI Express, but
layers three protocols on that signalling (CXL.io, CXL.cache, and