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authorBen Widawsky <ben.widawsky@intel.com>2022-01-24 03:29:31 +0300
committerDan Williams <dan.j.williams@intel.com>2022-02-09 09:57:28 +0300
commit608135db1b790170d22848815c4671407af74e37 (patch)
tree56ac0d0db0c6169734ac12455f743c55918c3c41 /drivers/cxl
parentc3bca8d4bb3ff77b8784cdc794eb1f8f89b10fb5 (diff)
downloadlinux-608135db1b790170d22848815c4671407af74e37.tar.xz
cxl/core: Convert decoder range to resource
CXL decoders manage address ranges in a hierarchical fashion whereby a leaf is a unique subregion of its parent decoder (midlevel or root). It therefore makes sense to use the resource API for handling this. Reviewed-by: Dan Williams <dan.j.williams@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> (v1) Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> Link: https://lore.kernel.org/r/164298417191.3018233.5201055578165414714.stgit@dwillia2-desk3.amr.corp.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl')
-rw-r--r--drivers/cxl/acpi.c22
-rw-r--r--drivers/cxl/core/port.c23
-rw-r--r--drivers/cxl/cxl.h8
3 files changed, 35 insertions, 18 deletions
diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
index c656a49a11a9..da70f1836db6 100644
--- a/drivers/cxl/acpi.c
+++ b/drivers/cxl/acpi.c
@@ -108,10 +108,8 @@ static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg,
cxld->flags = cfmws_to_decoder_flags(cfmws->restrictions);
cxld->target_type = CXL_DECODER_EXPANDER;
- cxld->range = (struct range){
- .start = cfmws->base_hpa,
- .end = cfmws->base_hpa + cfmws->window_size - 1,
- };
+ cxld->platform_res = (struct resource)DEFINE_RES_MEM(cfmws->base_hpa,
+ cfmws->window_size);
cxld->interleave_ways = CFMWS_INTERLEAVE_WAYS(cfmws);
cxld->interleave_granularity = CFMWS_INTERLEAVE_GRANULARITY(cfmws);
@@ -121,14 +119,13 @@ static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg,
else
rc = cxl_decoder_autoremove(dev, cxld);
if (rc) {
- dev_err(dev, "Failed to add decoder for %#llx-%#llx\n",
- cfmws->base_hpa,
- cfmws->base_hpa + cfmws->window_size - 1);
+ dev_err(dev, "Failed to add decoder for %pr\n",
+ &cxld->platform_res);
return 0;
}
- dev_dbg(dev, "add: %s node: %d range %#llx-%#llx\n",
- dev_name(&cxld->dev), phys_to_target_node(cxld->range.start),
- cfmws->base_hpa, cfmws->base_hpa + cfmws->window_size - 1);
+ dev_dbg(dev, "add: %s node: %d range %pr\n", dev_name(&cxld->dev),
+ phys_to_target_node(cxld->platform_res.start),
+ &cxld->platform_res);
return 0;
}
@@ -270,10 +267,7 @@ static int add_host_bridge_uport(struct device *match, void *arg)
cxld->interleave_ways = 1;
cxld->interleave_granularity = PAGE_SIZE;
cxld->target_type = CXL_DECODER_EXPANDER;
- cxld->range = (struct range) {
- .start = 0,
- .end = -1,
- };
+ cxld->platform_res = (struct resource)DEFINE_RES_MEM(0, 0);
device_lock(&port->dev);
dport = list_first_entry(&port->dports, typeof(*dport), list);
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index c5e74c6f04e8..63c76cb2a2ec 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -46,8 +46,14 @@ static ssize_t start_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct cxl_decoder *cxld = to_cxl_decoder(dev);
+ u64 start;
- return sysfs_emit(buf, "%#llx\n", cxld->range.start);
+ if (is_root_decoder(dev))
+ start = cxld->platform_res.start;
+ else
+ start = cxld->decoder_range.start;
+
+ return sysfs_emit(buf, "%#llx\n", start);
}
static DEVICE_ATTR_ADMIN_RO(start);
@@ -55,8 +61,14 @@ static ssize_t size_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct cxl_decoder *cxld = to_cxl_decoder(dev);
+ u64 size;
+
+ if (is_root_decoder(dev))
+ size = resource_size(&cxld->platform_res);
+ else
+ size = range_len(&cxld->decoder_range);
- return sysfs_emit(buf, "%#llx\n", range_len(&cxld->range));
+ return sysfs_emit(buf, "%#llx\n", size);
}
static DEVICE_ATTR_RO(size);
@@ -546,6 +558,13 @@ int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map)
if (rc)
return rc;
+ /*
+ * Platform decoder resources should show up with a reasonable name. All
+ * other resources are just sub ranges within the main decoder resource.
+ */
+ if (is_root_decoder(dev))
+ cxld->platform_res.name = dev_name(dev);
+
return device_add(dev);
}
EXPORT_SYMBOL_NS_GPL(cxl_decoder_add, CXL);
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 38779409a419..bfd95acea66c 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -179,7 +179,8 @@ enum cxl_decoder_type {
* struct cxl_decoder - CXL address range decode configuration
* @dev: this decoder's device
* @id: kernel device name id
- * @range: address range considered by this decoder
+ * @platform_res: address space resources considered by root decoder
+ * @decoder_range: address space resources considered by midlevel decoder
* @interleave_ways: number of cxl_dports in this decode
* @interleave_granularity: data stride per dport
* @target_type: accelerator vs expander (type2 vs type3) selector
@@ -190,7 +191,10 @@ enum cxl_decoder_type {
struct cxl_decoder {
struct device dev;
int id;
- struct range range;
+ union {
+ struct resource platform_res;
+ struct range decoder_range;
+ };
int interleave_ways;
int interleave_granularity;
enum cxl_decoder_type target_type;