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authorDragos Bogdan <dragos.bogdan@analog.com>2019-05-16 10:04:43 +0300
committerVinod Koul <vkoul@kernel.org>2019-05-21 08:06:05 +0300
commit8add6cce98482da67e971addd7eae8f22f8e6c7a (patch)
treefb18916dad4ef0fdf4a1584bef234c0b1de8c947 /drivers/dma/dma-axi-dmac.c
parente40543931fe34d7808bf87398a0daca44c919d25 (diff)
downloadlinux-8add6cce98482da67e971addd7eae8f22f8e6c7a.tar.xz
dmaengine: axi-dmac: Add support for interleaved cyclic transfers
The DMAC HDL core supports interleaved & cyclic transfers. An example use-case for this mode is when the controller is used as a video DMA. This change sets the `cyclic` field to true, so that when the IRQ comes and the `axi_dmac_transfer_done()` callback is called (from the interrupt handler) the proper `vchan_cyclic_callback()` is called. This way the DMAEngine framework will process data correctly for interleaved + cyclic transfers. This doesn't fix anything. It's an enhancement to the driver. Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/dma/dma-axi-dmac.c')
-rw-r--r--drivers/dma/dma-axi-dmac.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/dma/dma-axi-dmac.c b/drivers/dma/dma-axi-dmac.c
index f32fdf21edbd..4d2cae0bebb5 100644
--- a/drivers/dma/dma-axi-dmac.c
+++ b/drivers/dma/dma-axi-dmac.c
@@ -562,6 +562,9 @@ static struct dma_async_tx_descriptor *axi_dmac_prep_interleaved(
desc->sg[0].y_len = 1;
}
+ if (flags & DMA_CYCLIC)
+ desc->cyclic = true;
+
return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
}