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| author | Peter Ujfalusi <peter.ujfalusi@ti.com> | 2020-07-17 15:09:03 +0300 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2020-07-27 11:53:03 +0300 |
| commit | daf4ad0499aa4f75c6f32493829acdbe48110b32 (patch) | |
| tree | 728566a2cd13a3e51da4857fdefc14682c2ddd0c /drivers/dma/ti/k3-udma.h | |
| parent | 44385c4171d03b1aa030f3f21a6fce2f6edcfdab (diff) | |
| download | linux-daf4ad0499aa4f75c6f32493829acdbe48110b32.tar.xz | |
dmaengine: ti: k3-udma: Query throughput level information from hardware
The CAP3 register contains information about the number of
HCHAN (High Capacity) and UCHAN (Ultra High Capacity) channels in UDMAP.
Based on this information the start indexes of the levels can be calculated
without a need of a table in the match data.
On am654 the CAP3 does not contain information about the number different
channels. Set up the tpl information based on the available documentation.
This change will allow to use the same compatible for different SoCs where
the only difference is the number of channel types.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Link: https://lore.kernel.org/r/20200717120903.8774-3-peter.ujfalusi@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/dma/ti/k3-udma.h')
| -rw-r--r-- | drivers/dma/ti/k3-udma.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/dma/ti/k3-udma.h b/drivers/dma/ti/k3-udma.h index 9534f0ca29f4..09c4529e013d 100644 --- a/drivers/dma/ti/k3-udma.h +++ b/drivers/dma/ti/k3-udma.h @@ -42,6 +42,8 @@ #define UDMA_CAP2_ECHAN_CNT(val) (((val) >> 9) & 0x1ff) #define UDMA_CAP2_RCHAN_CNT(val) (((val) >> 18) & 0x1ff) #define UDMA_CAP3_RFLOW_CNT(val) ((val) & 0x3fff) +#define UDMA_CAP3_HCHAN_CNT(val) (((val) >> 14) & 0x1ff) +#define UDMA_CAP3_UCHAN_CNT(val) (((val) >> 23) & 0x1ff) /* UDMA_CHAN_RT_CTL_REG */ #define UDMA_CHAN_RT_CTL_EN BIT(31) |