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authorJean-Francois Moine <moinejf@free.fr>2016-04-22 09:14:33 +0300
committerVinod Koul <vinod.koul@intel.com>2016-04-26 06:39:28 +0300
commit128fe7e9a0b99da1d7346528526bd424f705774b (patch)
tree084273a5dc765353ecda9e3eff10c439b61bea9e /drivers/dma
parentf55532a0c0b8bb6148f4e07853b876ef73bc69ca (diff)
downloadlinux-128fe7e9a0b99da1d7346528526bd424f705774b.tar.xz
dmaengine: sun6i: Fix the access of the IRQ register
The IRQ register number is computed, but this number was not used and the register was the one indexed by the channel index instead. Then, only the first DMA channel was working. Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Jean-Francois Moine <moinejf@free.fr> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'drivers/dma')
-rw-r--r--drivers/dma/sun6i-dma.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
index 2db12e493c53..2ec320dc68b3 100644
--- a/drivers/dma/sun6i-dma.c
+++ b/drivers/dma/sun6i-dma.c
@@ -381,9 +381,9 @@ static int sun6i_dma_start_desc(struct sun6i_vchan *vchan)
irq_reg = pchan->idx / DMA_IRQ_CHAN_NR;
irq_offset = pchan->idx % DMA_IRQ_CHAN_NR;
- irq_val = readl(sdev->base + DMA_IRQ_EN(irq_offset));
+ irq_val = readl(sdev->base + DMA_IRQ_EN(irq_reg));
irq_val |= DMA_IRQ_QUEUE << (irq_offset * DMA_IRQ_CHAN_WIDTH);
- writel(irq_val, sdev->base + DMA_IRQ_EN(irq_offset));
+ writel(irq_val, sdev->base + DMA_IRQ_EN(irq_reg));
writel(pchan->desc->p_lli, pchan->base + DMA_CHAN_LLI_ADDR);
writel(DMA_CHAN_ENABLE_START, pchan->base + DMA_CHAN_ENABLE);