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authorMohan Kumar <mkumard@nvidia.com>2023-01-02 09:48:44 +0300
committerVinod Koul <vkoul@kernel.org>2023-01-18 15:04:36 +0300
commit9c7e355ccbb33d239360c876dbe49ad5ade65b47 (patch)
treedf3d839aaee106980d4a27f211bcc4c5aaee7704 /drivers/dma
parent57054fe516d59d03a7bcf1888e82479ccc244f87 (diff)
downloadlinux-9c7e355ccbb33d239360c876dbe49ad5ade65b47.tar.xz
dmaengine: tegra210-adma: fix global intr clear
The current global interrupt clear programming register offset was not correct. Fix the programming with right offset Fixes: ded1f3db4cd6 ("dmaengine: tegra210-adma: prepare for supporting newer Tegra chips") Cc: stable@vger.kernel.org Signed-off-by: Mohan Kumar <mkumard@nvidia.com> Link: https://lore.kernel.org/r/20230102064844.31306-1-mkumard@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/dma')
-rw-r--r--drivers/dma/tegra210-adma.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/dma/tegra210-adma.c b/drivers/dma/tegra210-adma.c
index ae39b52012b2..79da93cc77b6 100644
--- a/drivers/dma/tegra210-adma.c
+++ b/drivers/dma/tegra210-adma.c
@@ -221,7 +221,7 @@ static int tegra_adma_init(struct tegra_adma *tdma)
int ret;
/* Clear any interrupts */
- tdma_write(tdma, tdma->cdata->global_int_clear, 0x1);
+ tdma_write(tdma, tdma->cdata->ch_base_offset + tdma->cdata->global_int_clear, 0x1);
/* Assert soft reset */
tdma_write(tdma, ADMA_GLOBAL_SOFT_RESET, 0x1);