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authorQiuxu Zhuo <qiuxu.zhuo@intel.com>2019-06-13 11:40:27 +0300
committerTony Luck <tony.luck@intel.com>2019-06-20 21:44:36 +0300
commit5c5d3ac2064ae2466c81d40186bcc09b2d5b7892 (patch)
tree9cd8aea5412da7b0a5b99cad41ad58c310327f5a /drivers/edac
parent40d796243478e0d072a7e637e7558c3c8216b60a (diff)
downloadlinux-5c5d3ac2064ae2466c81d40186bcc09b2d5b7892.tar.xz
EDAC, i10nm: Add Intel additional Ice-Lake support
Two new CPU models share the same memory controller architecture with Jacobsville/Tremont, so can use the same i10nm EDAC driver. Add ICX and ICX-D CPU model numbers for EDAC support. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'drivers/edac')
-rw-r--r--drivers/edac/i10nm_base.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/edac/i10nm_base.c b/drivers/edac/i10nm_base.c
index 6f06aec4877c..48c6cecc9683 100644
--- a/drivers/edac/i10nm_base.c
+++ b/drivers/edac/i10nm_base.c
@@ -124,6 +124,8 @@ static int i10nm_get_all_munits(void)
static const struct x86_cpu_id i10nm_cpuids[] = {
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_TREMONT_X, 0, 0 },
+ { X86_VENDOR_INTEL, 6, INTEL_FAM6_ICELAKE_X, 0, 0 },
+ { X86_VENDOR_INTEL, 6, INTEL_FAM6_ICELAKE_XEON_D, 0, 0 },
{ }
};
MODULE_DEVICE_TABLE(x86cpu, i10nm_cpuids);