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authorSherry Sun <sherry.sun@nxp.com>2022-04-27 04:51:36 +0300
committerBorislav Petkov <bp@suse.de>2022-07-22 15:31:30 +0300
commitbe76ceaf03bc04e74be5e28f608316b73c2b04ad (patch)
tree5a9fc74eb571e14395f6e325812fd588852c1404 /drivers/edac
parentff6992735ade75aae3e35d16b17da1008d753d28 (diff)
downloadlinux-be76ceaf03bc04e74be5e28f608316b73c2b04ad.tar.xz
EDAC/synopsys: Use the correct register to disable the error interrupt on v3 hw
v3.x Synopsys EDAC DDR doesn't have the QOS Interrupt register. Use the ECC Clear Register to disable the error interrupts instead. Fixes: f7824ded4149 ("EDAC/synopsys: Add support for version 3 of the Synopsys EDAC DDR") Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Shubhrajyoti Datta <Shubhrajyoti.datta@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Cc: <stable@vger.kernel.org> Link: https://lore.kernel.org/r/20220427015137.8406-2-sherry.sun@nxp.com
Diffstat (limited to 'drivers/edac')
-rw-r--r--drivers/edac/synopsys_edac.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c
index 1cee64b80a7e..1e38b677d8fd 100644
--- a/drivers/edac/synopsys_edac.c
+++ b/drivers/edac/synopsys_edac.c
@@ -852,8 +852,11 @@ static void enable_intr(struct synps_edac_priv *priv)
static void disable_intr(struct synps_edac_priv *priv)
{
/* Disable UE/CE Interrupts */
- writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
- priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
+ if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
+ writel(0x0, priv->baseaddr + ECC_CLR_OFST);
+ else
+ writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
+ priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
}
static int setup_irq(struct mem_ctl_info *mci,