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authorMichal Simek <michal.simek@xilinx.com>2013-06-03 16:31:18 +0400
committerLinus Walleij <linus.walleij@linaro.org>2013-06-17 09:46:18 +0400
commitcc090d61d1a88f30f2fb75a91bce684ad1bd2e94 (patch)
tree03ad01257776488dea75669bf3c760741eca01df /drivers/gpio
parent74600ee017557b2ebb669e45237f655e9e2fbac8 (diff)
downloadlinux-cc090d61d1a88f30f2fb75a91bce684ad1bd2e94.tar.xz
GPIO: xilinx: Use __raw_readl/__raw_writel IO functions
This driver can be used on Xilinx ARM Zynq platform where in_be32/out_be32 functions are not implemented. Use __raw_readl/__raw_writel functions which are implemented on Microblaze and PowerPC. For ARM readl/writel functions are used instead. The correct way how to implement this is to detect endians directly on IP. But for the gpio case without interrupt connected(it means without interrupt logic) there are just 2 registers data and tristate where auto detection can't be done. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/gpio')
-rw-r--r--drivers/gpio/gpio-xilinx.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/gpio/gpio-xilinx.c b/drivers/gpio/gpio-xilinx.c
index 626eaa876f09..791ddaedbfb4 100644
--- a/drivers/gpio/gpio-xilinx.c
+++ b/drivers/gpio/gpio-xilinx.c
@@ -30,8 +30,13 @@
#define XGPIO_CHANNEL_OFFSET 0x8
/* Read/Write access to the GPIO registers */
-#define xgpio_readreg(offset) in_be32(offset)
-#define xgpio_writereg(offset, val) out_be32(offset, val)
+#ifdef CONFIG_ARCH_ZYNQ
+# define xgpio_readreg(offset) readl(offset)
+# define xgpio_writereg(offset, val) writel(val, offset)
+#else
+# define xgpio_readreg(offset) __raw_readl(offset)
+# define xgpio_writereg(offset, val) __raw_writel(val, offset)
+#endif
/**
* struct xgpio_instance - Stores information about GPIO device