Merge tag 'drm-next-2021-04-30' of git://anongit.freedesktop.org/drm/drm

Pull more drm updates from Dave Airlie:
 "Looks like I missed a tegra feature request for next, but should still
  be fine since it's pretty self contained.

  Apart from that got a set of i915 and amdgpu fixes as per usual along
  with a few misc fixes.

  tegra:
   - Tegra186 hardware cursor support
   - better capability reporting for different SoC
   - better framebuffer modifier support
   - host1x fixes

  ttm:
   - fix unswappable BO handling

  efifb:
   - check for PCI before using it

  amdgpu:
   - Fixes for Aldebaran
   - Display LTTPR fixes
   - eDP fixes
   - Fixes for Vangogh
   - RAS fixes
   - ASPM support
   - Renoir SMU fixes
   - Modifier fixes
   - Misc code cleanups
   - Freesync fixes

  i915:
   - Several fixes to GLK handling in recent display refactoring
   - Rare watchdog timer race fix
   - Cppcheck redundant condition fix
   - Overlay error code propagation fix
   - Documentation fix
   - gvt: Remove one unused function warning
   - gvt: Fix intel_gvt_init_device() return type
   - gvt: Remove one duplicated register accessible check"

* tag 'drm-next-2021-04-30' of git://anongit.freedesktop.org/drm/drm: (111 commits)
  efifb: Check efifb_pci_dev before using it
  drm/i915: Fix docbook descriptions for i915_gem_shrinker
  drm/i915: fix an error code in intel_overlay_do_put_image()
  drm/i915/display/psr: Fix cppcheck warnings
  drm/i915: Disable LTTPR detection on GLK once again
  drm/i915: Restore lost glk ccs w/a
  drm/i915: Restore lost glk FBC 16bpp w/a
  drm/i915: Take request reference before arming the watchdog timer
  drm/ttm: fix error handling if no BO can be swapped out v4
  drm/i915/gvt: Remove duplicated register accessible check
  drm/amdgpu/gmc9: remove dummy read workaround for newer chips
  drm/amdgpu: Add mem sync flag for IB allocated by SA
  drm/amdgpu: Fix SDMA RAS error reporting on Aldebaran
  drm/amdgpu: Reset RAS error count and status regs
  Revert "drm/amdgpu: workaround the TMR MC address issue (v2)"
  drm/amd/display: 3.2.132
  drm/amd/display: [FW Promotion] Release 0.0.62
  drm/amd/display: add helper for enabling mst stream features
  drm/amd/display: Report Proper Quantization Range in AVI Infoframe
  drm/amd/display: Fix call to pass bpp in 16ths of a bit
  ...

1 files changed, 10 insertions, 14 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 9e769cf6095b..a09483beb968 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -328,8 +328,12 @@ psp_cmd_submit_buf(struct psp_context *psp,
 
 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
 				 struct psp_gfx_cmd_resp *cmd,
-				 uint64_t tmr_mc, uint32_t size)
+				 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo)
 {
+	struct amdgpu_device *adev = psp->adev;
+	uint32_t size = amdgpu_bo_size(tmr_bo);
+	uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo);
+
 	if (amdgpu_sriov_vf(psp->adev))
 		cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
 	else
@@ -337,6 +341,9 @@ static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
 	cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
 	cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
 	cmd->cmd.cmd_setup_tmr.buf_size = size;
+	cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1;
+	cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa);
+	cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa);
 }
 
 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
@@ -407,16 +414,6 @@ static int psp_tmr_init(struct psp_context *psp)
 				      AMDGPU_GEM_DOMAIN_VRAM,
 				      &psp->tmr_bo, &psp->tmr_mc_addr, pptr);
 
-	/* workaround the tmr_mc_addr:
-	 * PSP requires an address in FB aperture. Right now driver produce
-	 * tmr_mc_addr in the GART aperture. Convert it back to FB aperture
-	 * for PSP. Will revert it after we get a fix from PSP FW.
-	 */
-	if (psp->adev->asic_type == CHIP_ALDEBARAN) {
-		psp->tmr_mc_addr -= psp->adev->gmc.fb_start;
-		psp->tmr_mc_addr += psp->adev->gmc.fb_start_original;
-	}
-
 	return ret;
 }
 
@@ -466,8 +463,7 @@ static int psp_tmr_load(struct psp_context *psp)
 	if (!cmd)
 		return -ENOMEM;
 
-	psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr,
-			     amdgpu_bo_size(psp->tmr_bo));
+	psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo);
 	DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
 		 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
 
@@ -561,7 +557,7 @@ static int psp_boot_config_set(struct amdgpu_device *adev)
 	struct psp_context *psp = &adev->psp;
 	struct psp_gfx_cmd_resp *cmd = psp->cmd;
 
-	if (adev->asic_type != CHIP_SIENNA_CICHLID)
+	if (adev->asic_type != CHIP_SIENNA_CICHLID || amdgpu_sriov_vf(adev))
 		return 0;
 
 	memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));