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authorYang Wang <KevinYang.Wang@amd.com>2022-09-09 06:06:50 +0300
committerAlex Deucher <alexander.deucher@amd.com>2022-09-13 19:56:16 +0300
commitcd3a49af58c23dd5ffa1d4d5a120ee2354d2e8d8 (patch)
tree88c4ee7019cc15b86adaa54063d806c6265959c9 /drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
parent34dfca890835ca9f4a59c8a2ff6be8c0513637c7 (diff)
downloadlinux-cd3a49af58c23dd5ffa1d4d5a120ee2354d2e8d8.tar.xz
drm/amdgpu: change the alignment size of TMR BO to 1M
align TMR BO size TO tmr size is not necessary, modify the size to 1M to avoid re-create BO fail when serious VRAM fragmentation. v2: add new macro PSP_TMR_ALIGNMENT for TMR BO alignment size Signed-off-by: Yang Wang <KevinYang.Wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index c32b74bd970f..e593e8c2a54d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -36,6 +36,7 @@
#define PSP_CMD_BUFFER_SIZE 0x1000
#define PSP_1_MEG 0x100000
#define PSP_TMR_SIZE(adev) ((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000)
+#define PSP_TMR_ALIGNMENT 0x100000
#define PSP_FW_NAME_LEN 0x24
enum psp_shared_mem_size {