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authorXiangliang Yu <Xiangliang.Yu@amd.com>2017-02-16 10:07:06 +0300
committerAlex Deucher <alexander.deucher@amd.com>2017-03-30 06:53:16 +0300
commitd1aad4d8a4bc8bdb7132baf9361d0ee9b2f6a944 (patch)
tree6ce9ab6a1e6f913a8f0eb8b315da6258df0c6291 /drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
parent59a82d7d69cf63da641314384b1e691aa8c12999 (diff)
downloadlinux-d1aad4d8a4bc8bdb7132baf9361d0ee9b2f6a944.tar.xz
drm/amdgpu/virt: fix typo
When send messages to hypervior, the messages format should be is idh_request, not idh_event. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Monk Liu <Monk.Liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c16
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
index 98cbcd9217e2..3164d61aaa9e 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
@@ -350,13 +350,13 @@ static void xgpu_vi_mailbox_set_valid(struct amdgpu_device *adev, bool val)
}
static void xgpu_vi_mailbox_trans_msg(struct amdgpu_device *adev,
- enum idh_event event)
+ enum idh_request req)
{
u32 reg;
reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0);
reg = REG_SET_FIELD(reg, MAILBOX_MSGBUF_TRN_DW0,
- MSGBUF_DATA, event);
+ MSGBUF_DATA, req);
WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0, reg);
xgpu_vi_mailbox_set_valid(adev, true);
@@ -458,20 +458,20 @@ static int xgpu_vi_request_reset(struct amdgpu_device *adev)
static int xgpu_vi_request_full_gpu_access(struct amdgpu_device *adev,
bool init)
{
- enum idh_event event;
+ enum idh_request req;
- event = init ? IDH_REQ_GPU_INIT_ACCESS : IDH_REQ_GPU_FINI_ACCESS;
- return xgpu_vi_send_access_requests(adev, event);
+ req = init ? IDH_REQ_GPU_INIT_ACCESS : IDH_REQ_GPU_FINI_ACCESS;
+ return xgpu_vi_send_access_requests(adev, req);
}
static int xgpu_vi_release_full_gpu_access(struct amdgpu_device *adev,
bool init)
{
- enum idh_event event;
+ enum idh_request req;
int r = 0;
- event = init ? IDH_REL_GPU_INIT_ACCESS : IDH_REL_GPU_FINI_ACCESS;
- r = xgpu_vi_send_access_requests(adev, event);
+ req = init ? IDH_REL_GPU_INIT_ACCESS : IDH_REL_GPU_FINI_ACCESS;
+ r = xgpu_vi_send_access_requests(adev, req);
return r;
}