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authorYifan Zha <Yifan.Zha@amd.com>2022-10-25 09:46:11 +0300
committerAlex Deucher <alexander.deucher@amd.com>2022-11-01 18:45:50 +0300
commite1a29b28e70457549149d3b2c82e4333d68ac49d (patch)
tree02697ce0b02366fad7dbbd9ab07325df7867699b /drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
parent47a7470bb2ca2d2ccbd945082e5ebf0279a33fe5 (diff)
downloadlinux-e1a29b28e70457549149d3b2c82e4333d68ac49d.tar.xz
drm/amdgpu: Skip access SDMA0_F32_CNTL in sdma_v6_0_enable under SRIOV
[Why] SDMA0_F32_CNTL is a PF_only regitser which will be blocked by L1. RLCG will not program the register as well. [How] Skip to program SDMA0_F32_CNTL under SRIOV VF. Signed-off-by: Yifan Zha <Yifan.Zha@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
index d9ae69be5ea4..049c26a45d85 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
@@ -455,6 +455,9 @@ static void sdma_v6_0_enable(struct amdgpu_device *adev, bool enable)
sdma_v6_0_rlc_stop(adev);
}
+ if (amdgpu_sriov_vf(adev))
+ return;
+
for (i = 0; i < adev->sdma.num_instances; i++) {
f32_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));
f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);