summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
diff options
context:
space:
mode:
authorJay Cornwall <Jay.Cornwall@amd.com>2017-08-16 06:00:14 +0300
committerOded Gabbay <oded.gabbay@gmail.com>2017-08-16 06:00:14 +0300
commitaf68d87cac0664c9118e76727e4273eab56deb83 (patch)
treeefa137d188a0a008f6b8ec41dd76a78664cb63bc /drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
parent4ebc7182743a4bef47cdd9d3e9f08cff943faa4f (diff)
downloadlinux-af68d87cac0664c9118e76727e4273eab56deb83.tar.xz
drm/amdkfd: Clamp EOP queue size correctly on Gfx8
Gfx8 HW incorrectly clamps CP_HQD_EOP_CONTROL.EOP_SIZE, which can lead to scheduling deadlock due to SE EOP done counter overflow. Enforce a EOP queue size limit which prevents the CP from sending more than 0xFF events at a time. Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c')
-rw-r--r--drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c11
1 files changed, 9 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
index f4c8c2324d77..98a930e9720f 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
@@ -135,8 +135,15 @@ static int __update_mqd(struct mqd_manager *mm, void *mqd,
3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT |
mtype << CP_HQD_IB_CONTROL__MTYPE__SHIFT;
- m->cp_hqd_eop_control |=
- ffs(q->eop_ring_buffer_size / sizeof(unsigned int)) - 1 - 1;
+ /*
+ * HW does not clamp this field correctly. Maximum EOP queue size
+ * is constrained by per-SE EOP done signal count, which is 8-bit.
+ * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit
+ * more than (EOP entry count - 1) so a queue size of 0x800 dwords
+ * is safe, giving a maximum field value of 0xA.
+ */
+ m->cp_hqd_eop_control |= min(0xA,
+ ffs(q->eop_ring_buffer_size / sizeof(unsigned int)) - 1 - 1);
m->cp_hqd_eop_base_addr_lo =
lower_32_bits(q->eop_ring_buffer_address >> 8);
m->cp_hqd_eop_base_addr_hi =