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author | Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> | 2021-02-17 19:32:10 +0300 |
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committer | Alex Deucher <alexander.deucher@amd.com> | 2021-03-24 06:33:32 +0300 |
commit | 443dfba02483872384354bc0e62c656e3f82b6a9 (patch) | |
tree | bc02acaee8c12fb6877b2dda26c06793e7c340ea /drivers/gpu/drm/amd/display/dc/dce100 | |
parent | 8ee0fea4baf90e43efe2275de208a7809f9985bc (diff) | |
download | linux-443dfba02483872384354bc0e62c656e3f82b6a9.tar.xz |
drm/amd/display: fix dcn3+ bw validation soc param update sequence
SOC needs to be updated to the WM set A values before validation
happens.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce100')
0 files changed, 0 insertions, 0 deletions