diff options
| author | Taimur Hassan <syed.hassan@amd.com> | 2020-09-10 17:13:42 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-09-22 19:28:56 +0300 |
| commit | 99d1437aa0ac1f598e9aabca8bf0e8a40c38f8a1 (patch) | |
| tree | efdd809c796cd7c0c2cbda913f3c71ebd3a055fa /drivers/gpu/drm/amd/display/dc/dcn10 | |
| parent | a9edc81564c92b4d86670b722bbe8906e0dfd934 (diff) | |
| download | linux-99d1437aa0ac1f598e9aabca8bf0e8a40c38f8a1.tar.xz | |
drm/amd/display: Check for flip pending before locking pipes.
[Why]
When running a game/benchmark with v-sync disabled, disabling a plane
(which is v-sync) can cause an underflow. This is due to flips that are
pending before pipe locking being applied after locks are released and
pipes have been re-arranged or disconnected. This can potentially apply
a flip on the incorrect pipe.
[How]
Check that any pending flips are cleared before locking any pipes to
ensure flips are applied on the correct pipes.
Signed-off-by: Taimur Hassan <syed.hassan@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 12 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h | 2 |
2 files changed, 11 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index d0f3bf953d02..79fe9571cf5d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -2761,7 +2761,7 @@ static struct pipe_ctx *dcn10_find_top_pipe_for_stream( return NULL; } -bool dcn10_disconnect_pipes( +void dcn10_disconnect_pipes( struct dc *dc, struct dc_state *context) { @@ -2772,6 +2772,10 @@ bool dcn10_disconnect_pipes( bool mpcc_disconnected = false; struct pipe_ctx *old_pipe; struct pipe_ctx *new_pipe; + + dc->hwss.wait_for_pending_cleared(dc, context); + dc->hwss.interdependent_update_lock(dc, context, true); + DC_LOGGER_INIT(dc->ctx->logger); /* Set pipe update flags and lock pipes */ @@ -2874,7 +2878,11 @@ bool dcn10_disconnect_pipes( } } } - return mpcc_disconnected; + + dc->hwss.interdependent_update_lock(dc, context, false); + + if (mpcc_disconnected) + dc->hwss.wait_for_pending_cleared(dc, context); } void dcn10_wait_for_pending_cleared(struct dc *dc, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h index e5691e499023..9a0f7a8a85cd 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h @@ -194,7 +194,7 @@ void dcn10_get_surface_visual_confirm_color( void dcn10_get_hdr_visual_confirm_color( struct pipe_ctx *pipe_ctx, struct tg_color *color); -bool dcn10_disconnect_pipes( +void dcn10_disconnect_pipes( struct dc *dc, struct dc_state *context); |