diff options
| author | Samson Tam <Samson.Tam@amd.com> | 2022-03-04 17:34:58 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-06-03 23:45:01 +0300 |
| commit | 327f79d7a1d2dcc10aeda05983c4d1532dd0830a (patch) | |
| tree | 25d1b2543deb5b92596fa81e3f534072309d6cbe /drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h | |
| parent | 0c9ed6044c5d08562d38d56e94279badef39e4c7 (diff) | |
| download | linux-327f79d7a1d2dcc10aeda05983c4d1532dd0830a.tar.xz | |
drm/amd/display: Updates for OTG and DCCG clocks
Use DTBCLK for valid pixel clock generation
Signed-off-by: Samson Tam <Samson.Tam@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h index e07b317ed3f4..5e57c39235fa 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h @@ -245,6 +245,7 @@ SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\ SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\ SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\ + SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE_MANUAL, mask_sh),\ SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\ SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh) |