diff options
| author | Dillon Varone <dillon.varone@amd.com> | 2022-04-18 21:39:20 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-06-03 23:45:00 +0300 |
| commit | be77243327d962a87bcf03615bae12d73efb9b7c (patch) | |
| tree | 09a80c472aff626b9e24be942bb0940e609fff4d /drivers/gpu/drm/amd/display/dc/dcn321 | |
| parent | 1d6c363330834fa534c1c7ee01620ff134aade1f (diff) | |
| download | linux-be77243327d962a87bcf03615bae12d73efb9b7c.tar.xz | |
drm/amd/display: set dram speed for all states
[WHY?]
If higher states have memory speed set to 0 MT/s currently they do not get set
to the highest value which can cause validation failures.
[HOW?]
Set unpopulated higher states to max value.
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn321')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c index 0b420466b6dd..27d3aa7d751f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c @@ -1899,7 +1899,6 @@ static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *b dcn3_21_soc.clock_limits[i].state = i; dcn3_21_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; dcn3_21_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; - dcn3_21_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; /* Fill all states with max values of all these clocks */ dcn3_21_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; @@ -1918,6 +1917,11 @@ static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *b else dcn3_21_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz; + if (!dram_speed_mts[i] && i > 0) + dcn3_21_soc.clock_limits[i].dram_speed_mts = dcn3_21_soc.clock_limits[i-1].dram_speed_mts; + else + dcn3_21_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; + /* These clocks cannot come from bw_params, always fill from dcn3_21_soc[0] */ /* PHYCLK_D18, PHYCLK_D32 */ dcn3_21_soc.clock_limits[i].phyclk_d18_mhz = dcn3_21_soc.clock_limits[0].phyclk_d18_mhz; |