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| author | Jaehyun Chung <jaehyun.chung@amd.com> | 2019-08-19 23:45:05 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-09-14 02:03:06 +0300 |
| commit | 785908cf19c9eb4803f6bf9c0a7447dc3661d5c3 (patch) | |
| tree | d8fe2db7d24c43add6b869ee2d005952a46a3f4c /drivers/gpu/drm/amd/display/dc/dsc | |
| parent | 119630061e72e6512ee8911b473cfacb6b211c53 (diff) | |
| download | linux-785908cf19c9eb4803f6bf9c0a7447dc3661d5c3.tar.xz | |
drm/amd/display: OTC underflow fix
[Why] Underflow occurs on some display setups(repro'd on 3x4K HDR) on boot,
mode set, and hot-plugs with. Underflow occurs because mem clk
is not set high after disabling pstate switching. This behaviour occurs
because some calculations assumed displays were synchronized.
[How] Add a condition to check if timing sync is disabled so that
synchronized vblank can be set to false.
Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com>
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dsc')
0 files changed, 0 insertions, 0 deletions