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authorBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>2020-05-21 19:32:53 +0300
committerAlex Deucher <alexander.deucher@amd.com>2020-07-01 08:59:14 +0300
commit4d55b0dd1cdd8535ffd6057f210465575117d807 (patch)
treefa71c4f5002239f2af3941270bdb519203eba520 /drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
parentbe547111d2be16e81dc2d9669cf3caa3675fa55d (diff)
downloadlinux-4d55b0dd1cdd8535ffd6057f210465575117d807.tar.xz
drm/amd/display: Add DCN3 CLK_MGR
Adds support for handling of clocking relevant to the DCN3 block Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h')
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
index 9311d0de377f..c3c151be7d03 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
@@ -101,6 +101,12 @@ enum dentist_divider_range {
CLK_SRI(CLK3_CLK_PLL_REQ, CLK3, 0), \
CLK_SRI(CLK3_CLK2_DFS_CNTL, CLK3, 0)
+#ifdef CONFIG_DRM_AMD_DC_DCN3_0
+// TODO:
+#define CLK_REG_LIST_DCN3() \
+ SR(DENTIST_DISPCLK_CNTL)
+#endif
+
#define CLK_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
@@ -167,6 +173,10 @@ struct clk_mgr_registers {
uint32_t CLK3_CLK2_DFS_CNTL;
uint32_t CLK3_CLK_PLL_REQ;
+#ifdef CONFIG_DRM_AMD_DC_DCN3_0
+ uint32_t CLK0_CLK2_DFS_CNTL;
+ uint32_t CLK0_CLK_PLL_REQ;
+#endif
uint32_t MP1_SMN_C2PMSG_67;
uint32_t MP1_SMN_C2PMSG_83;
uint32_t MP1_SMN_C2PMSG_91;
@@ -260,6 +270,10 @@ struct clk_mgr_internal {
enum dm_pp_clocks_state max_clks_state;
enum dm_pp_clocks_state cur_min_clks_state;
+#ifdef CONFIG_DRM_AMD_DC_DCN3_0
+
+ bool smu_present;
+#endif
};
struct clk_mgr_internal_funcs {